ICS932S202 Datasheet, PDF (1/14 Pages) Integrated Circuit Systems – Frequency Timing Generator for Differential PIIIType Dual-CPU Systems

Integrated
Circuit
Systems, Inc.
ICS932S202
Frequency Timing Generator for Differential PIII Type
Dual-CPU Systems
Recommended Application:
Serverwork HE-T, HE-SL & LE-T Chipsets
Output Features:
• 2 - CPUs @ 2.5V, up to 180MHz
• 2 - CPU chipset @ 2.5V, up to 180MHz
• 3 - IOAPIC @ 2.5V
• 3 - 3V66MHz @ 3.3V
• 11 - PCIs @ 3.3V
• 1 - 48MHz, @ 3.3V fixed
• 1 - 24/48MHz, @ 3.3V
• 2 - REF @ 3.3V
Features:
• Up to 180MHz frequency support
• Support power management: Power down Mode
from I²C programming.
• Spread spectrum for EMI control
± 0.25% center spread).
• Uses external 14.318MHz crystal
• 5 - FS pins for frequency select
Key Specifications:
• CPU Output Jitter: <150ps
• IOAPIC Output Jitter: <500ps
• 48MHz, 3V66, PCI Output Jitter: <500ps
• Ref Output Jitter. <1000ps
• CPU Output Skew: <175ps
• IOAPIC Output Skew <250ps
• PCI Output Skew: <500ps
• 3V66 Output Skew <250ps
• CPU to 3V66 Output Offset: 0.8 - 1.8ns (typ =
1.3ns)
• CPU to PCI Output Offset: 0.0 - 1.5ns (typ =
0.9ns)
• CPU to IOAPIC Output Offset: 1.5 - 4.0ns (typ =
2.0ns)
Block Diagram
PLL2
X1
XTAL
X2
OSC
PLL1
Spread
Spectrum
SEL24_48#
SDATA
SCLK
FS (4:0)
PD#
Control
Logic
Config.
Reg.
/2
CPU
DIVDER
IOAPIC
DIVDER
PCI
DIVDER
3V66
DIVDER
0600A—08/04/03
48MHz
24_48MHz
REF (1:0)
CPUCLK (1:0)
CPU_CSCLK (1:0)
IOAPIC (2:0)
PCICLK (10:0)
3V66 (2:0)
Pin Configuration
GNDREF
1
REF0
2
*SEL24_48#/REF1
3
VDDREF
4
X1
5
X2
6
GNDPCI
7
*FS0/PCICLK0
8
*FS1/PCICLK1
9
VDDPCI
10
*FS2/PCICLK2
11
*FS3/PCICLK3
12
GNDPCI
13
PCICLK4
14
PCICLK5
15
VDDPCI
16
PCICLK6
17
PCICLK7
18
GNDPCI
19
PCICLK8
20
PCICLK9
21
PCICLK10
22
VDDPCI
23
PD#
24
48
VDDLAPIC
47
IOAPIC0
46
IOAPIC1
45
GNDLAPIC
44
IOAPIC2
43
VDDLCPU
42
CPUCLK0
41
GNDLCPU
40
CPUCLK1
39
VDDLCPU
38
CPU_CSCLK0
37
CPU_CSCLK1
36
GNDLCPU
35
VDD66
34
3V66_0
33
3V66_1
32
3V66_2
31
GND66
30
SDATA
29
SCLK
28
VDD48
27
48MHz/FS4*
26
24_48MHz
25
GND48
48-pin SSOP
*120K ohm pull-up to VDD on indicated inputs.