ICS854054 Datasheet, PDF (1/13 Pages) Integrated Circuit Systems – DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER

Integrated
Circuit
Systems, Inc.
ICS854054
4:1
DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
GENERAL DESCRIPTION
The ICS854054 is a 4:1 Differential-to-LVDS Clock
ICS
Multiplexer which can operate up to 2.8GHz and
HiPerClockS™ _{is a member of the HiPerClockS™ family of High}
Performance Clock Solutions from ICS. The
ICS854054 has 4 selectable differential clock
inputs. The PCLK, nPCLK input pairs can accept LVPECL,
LVDS, CML or SSTL levels. The fully differential architec-
ture and low propagation delay make it ideal for use in clock
distribution circuits. The select pins have internal pulldown
resistors. The SEL1 pin is the most significant bit and the
binary number applied to the select pins will select the same
numbered data input (i.e., 00 selects PCLK0, nPCLK0).
FEATURES
• High speed 4:1 differential multiplexer
• One differential LVDS output
• Four selectable differential clock inputs
• PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
• Maximum output frequency: 2.8GHz
• Translates any single ended input signal to
LVDS levels with resistor bias on nPCLKx input
• Part-to-part skew: 375ps (maximum)
• Propagation delay: 700ps (maximum)
• Supply voltage range: 3.135V to 3.465V
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM
PCLK0
nPCLK0
PCLK1
nPCLK1
PCLK2
nPCLK2
PCLK3
nPCLK3
0 0(default)
01
10
11
PIN ASSIGNMENT
PCLK0 1
16 VDD
nPCLK0 2 15 Q
PCLK1 3 14 nQ
nPCLK1 4 13 GND
VDD 5
12 nPCLK3
SEL0 6 11 PCLK3
SEL1 7 10 nPCLK2
Q
GND 8
9 PCLK2
nQ
ICS854054
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm package body
G Package
Top View
SEL1 SEL0
854054AG
www.icst.com/products/hiperclocks.html
1
REV. A MARCH 29, 2006