ICS601-25 Datasheet, PDF (1/5 Pages) Integrated Circuit Systems – LOW PHASE NOISE 1 TO 5 CLOCK MULTIPLIER

ICS601-25
LOW PHASE NOISE 1 TO 5 CLOCK MULTIPLIER
Description
The ICS601-25 is a low-cost, low phase noise, high
performance clock synthesizer for applications which
require low phase noise, low jitter, and low skew fanout.
It is ICS’ lowest phase noise multiplier, and also the
lowest CMOS part in the industry. Using ICS’ patented
analong and digital Phase Locked Loop (PLL)
techniques, the chip accepts a 10-27 MHz crystal or
clock input, and produces output clocks up to 156 MHz.
Features
• Packaged in 20-pin SSOP
• Uses fundamental 10 - 27 MHz crystal or clock
• Output clocks up to 156 MHz
• Low phase noise: -132 dBc/Hz at 10 kHz
• Five low skew (<250 ps) outputs
• Low jitter - 18 ps one sigma at 125 MHz
• Full swing CMOS outputs with 25 mA drive capability
at TTL levels
• Powerdown mode lowers power consumption
• Advanced, low power, sub-micron CMOS process
• Industrial temperature version available
• Available in Pb (lead) free package
• Operating voltage of 3.3 V
Block Diagram
X1/ICLK
Crystal or
clock input X2
Reference
Divider
Crystal
Oscillator
Phase
Comparator
VDD
5
Charge
Pump
Loop
Filter
VCO
ROM Based
Multipliers
VCO
Divide
4
3
S3:0
GND
PD
CLK1
CLK2
CLK3
CLK4
CLK5
MDS 601-25 C
1
Revision 071505
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel [phone] ● www.icst.com