ICS162835 Datasheet, PDF (1/7 Pages) Integrated Circuit Systems – 18-Bit 3.3V Registered Buffer

Integrated
Circuit
Systems, Inc.
ICS162835
Advance Information
18-Bit 3.3V Registered Buffer
Recommended Applications:
• PC133 Registered Memory Module
• PC motherboards
• Servers and workstations
• Provides complete PC133 DIMM solution with
ICS2509, ICS2510 PLL.
Product Features:
• Meets JESD 82-2 specification
• Internal series resistors to reduce switching noise
• ±12 mA device capability
• Low voltage operation
- V_DD = 3.3 ± 0.3V
• 0.50 mm pitch, 56-Pin TSSOP package
Function Table¹
OE#
H
L
L
L
L
L
L
Notes:
Inputs
LE
CLK
X
X
H
X
H
X
L
↑
L
↑
L
H
L
L
Outputs
Ax
Yx
X
Z
L
L
H
H
L
L
H
H
X
Y₀₍₂₎
X
Y₀₍₃₎
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-Impedance
↑ = LOW-to-HIGH Transition
2. Output level before the indicated steady-state
input conditions were established, provided that
CLK is HIGH before LE went LOW.
3. Output level before the indicated steady-state
input conditions were established.
Block Diagram
OE#
CLK
LE
A1
1D
Y1
C1
CK
Pin Configurations
NC
1
NC
2
Y1
3
GND
4
Y2
5
Y3
6
VDD
7
Y4
8
Y5
9
Y6 10
GND 11
Y7 12
Y8 13
Y9 14
Y10 15
Y11 16
Y12 17
GND 18
Y13 19
Y14 20
Y15 21
VDD 22
Y16 23
Y17 24
GND 25
Y18 26
OE# 27
LE 28
56
GND
55
NC
54
A1
53
GND
52
A2
51
A3
50
VDD
49
A4
48
A5
47
A6
46
GND
45
A7
44
A8
43
A9
42
A10
41
A11
40
A12
39
GND
38
A13
37
A14
36
A15
35
VDD
34
A16
33
A17
32
GND
31
A18
30
CLK
29
GND
56-Pin TSSOP
6.10 mm. Body, 0.50 mm. pitch
Pin Description
Pin Names Description
OE#
Output Enable Input (Active Low)
CLK
Clock Input
LE
Latch Enable Input
Ax
Data Input
Yx
Data Outputs
V_DD
GND
Supply Voltage
Ground
0713—09/23/02
To 17 Other Channels
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.