IC61SF6432 Datasheet, PDF (9/17 Pages) Integrated Circuit Solution Inc – 64K x 32 Flow Through Sync. SRAM

IC61SF6432
READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol Parameter
-9
-10
Min. Max.
Min. Max.
Unit
tKC
Cycle Time
13 —
15 —
ns
tKH
Clock High Time
6—
6
—
ns
tKL
Clock Low Time
6—
6
—
ns
tKQ
Clock Access Time
—9
— 10
ns
tKQX⁽²⁾
Clock High to Output Invalid
2—
2
—
ns
tKQLZ^(2,3) Clock High to Output Low-Z
0—
0
—
ns
tKQHZ^(2,3) Clock High to Output High-Z
26
2
6
ns
tAS
Address Setup Time
2.5 —
2.5 —
ns
tSS
Address Status Setup Time
2.5 —
2.5 —
ns
tWS
Write Setup Time
2.5 —
2.5 —
ns
tCES
Chip Enable Setup Time
2.5 —
2.5 —
ns
tAVS
Address Advance Setup Time
2.5 —
2.5 —
ns
tAH
Address Hold Time
1—
1
—
ns
tSH
Address Status Hold Time
0.5 —
0.5 —
ns
tWH
Write Hold Time
0.5 —
0.5 —
ns
tCEH
Chip Enable Hold Time
0.5 —
0.5 —
ns
tAVH
Address Advance Hold Time
0.5 —
0.5 —
ns
tCFG
Configuration Setup⁽¹⁾
66.7 —
80 —
ns
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
Integrated Circuit Solution Inc.
9
SSR017-0A 09/13/2001