IC61SF6432 Datasheet, PDF (14/17 Pages) Integrated Circuit Solution Inc – 64K x 32 Flow Through Sync. SRAM

IC61SF6432
READ/WRITE CYCLE TIMING: FLOW-THROUGH
CLK
ADSP
ADSC
tKC
tKH
tKL
tSS
tSH
tSS
tSH
ADSP is blocked by CE inactive
ADV
A15-A0
GW
BWE
BW4-BW1
CE
CE2
CE2
OE
DATAOUT
DATAIN
tAS
tAH
RD1
WR1
RD2
RD3
tWS
tWH
tWS
tWH
tCES
tCEH
tWS
tWH
WR1
CE Masks ADSP
tCES
tCEH
tCES
tCEH
CE2 and CE2 only sampled with ADSP or ADSC
tOEHZ
Unselected with CE2
High-Z
tKQLZ
tKQ
High-Z
tOEQX
1a
2a
2b
2c
2d
tKQX
tKQHZ
1a
tDS
tDH
Single Read
Flow-through
Single Write
Burst Read
tKQX
tKQHZ
Unselected
14
Integrated Circuit Solution Inc.
SSR017-0A 09/13/2001