IS61LV12816 Datasheet, PDF (7/11 Pages) Integrated Circuit Solution Inc – 128K x 16 HIGH-SPEED CMOS STATIC RAM

IS61LV12816
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,3) (Over Operating Range)
Symbol Parameter
-8
Min. Max.
-10
Min. Max.
-12
Min. Max.
-15
Min. Max. Unit

tWC Write Cycle Time
8—
10 —
12 —
15 — ns
tSCE CE to Write End
7—
8—
8—
10 — ns
tAW Address Setup Time
to Write End
7—
8—
8—
10 — ns
tHA Address Hold from Write End 0 —
0—
0—
0 — ns
tSA Address Setup Time
0—
0—
0—
0 — ns
!
tPWB LB, UB Valid to End of Write 7 —
8—
9—
10 — ns
tPWE^" WE Pulse Width
7—
8—
9—
10 — ns
tSD Data Setup to Write End
4.5 —
5—
6—
7 — ns
"
tHD Data Hold from Write End
0—
0—
0—
0 — ns
tHZWE WE LOW to High-Z Output
tLZWE WE HIGH to Low-Z Output
—3
0—
—4
0—
—5
0—
— 6 ns
0 — ns
#
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
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3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
4.Tested with OE Hith.
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Integrated Circuit Solution, Inc.
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SR023_0C