IC61LV25616 Datasheet, PDF (7/11 Pages) Integrated Circuit Solution Inc – 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY

IC61LV25616
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,3) (Over Operating Range)
Symbol Parameter
-8
Min. Max.
-10
Min. Max.
-12
Min. Max.
-15
Min. Max. Unit
1
tWC Write Cycle Time
8—
10 —
12 —
15 — ns
tSCE CE to Write End
7—
8—
9—
10 — ns
tAW Address Setup Time
7—
8—
9—
10 — ns
2
to Write End
tHA Address Hold from Write End 0 —
0—
0—
0 — ns
tSA Address Setup Time
0—
0—
0—
0 — ns
3
tPWB LB, UB Valid to End of Write 7
—
8—
9—
10 — ns
tPWE WE Pulse Width
7—
8—
9—
10 — ns
tSD Data Setup to Write End
4.5 —
5—
6—
7 — ns
4
tHD Data Hold from Write End
0—
0—
0—
0 — ns
tHZWE⁽²⁾ WE LOW to High-Z Output
—
4
—5
—6
— 7 ns
tLZWE⁽²⁾ WE HIGH to Low-Z Output
3—
3—
3—
3 — ns
5
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to
6
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
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8
9
10
11
12
Integrated Circuit Solution Inc.
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AHSR022-0A 09/11/2001