IS61LV256 Datasheet, PDF (6/8 Pages) Integrated Circuit Solution Inc – 32K X 8 LOW VOLTAGE CMOS STATIC RAM

IS61LV256
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,2) (Over Operating Range)
Symbol Parameter
-8 ns
-10 ns
-12 ns
-15 ns
-20 ns
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tWC Write Cycle Time
8 — 10 — 12 — 15 — 20 — ns
tSCE CE to Write End
7 — 8 — 8 — 10 — 12 — ns
tAW Address Setup Time
to Write End
7 — 8 — 8 — 10 — 12 — ns
tHA Address Hold
from Write End
0 — 0 — 0 — 0 — 0 — ns
tSA Address Setup Time
0 — 0 — 0 — 0 — 0 — ns
tPWE1 WE Pulse Width(OE High) 7 — 10 — 12 — 15 — 20 — ns
tPWE2 WE Pulse Width(OE Low) 6.5 — 7 — 8 — 10 — 12 — ns
tSD Data Setup to Write End
4.5 — 5 — 6 — 7 — 10 — ns
tHD Data Hold from Write End
0—
0—
0—
0—
0 — ns
tHZWE^! WE LOW to High-Z Output — 3.5 — 4
—6
—7
—7
ns
tLZWE^! WE HIGH to Low-Z Output 0 —
0—
0—
0—
0 — ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse
levels of 0 to 3.0V and output loading specified in .igure 1.
2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid
states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and
Hold timing are referenced to the rising or falling edge of the signal that terminates the Write.
3. Tested with the load in .igure 2. Transition is measured ±500 mV from steady-state voltage. Not 100%
tested.
AC WAVE.ORMS
WRITE CYCLE NO. 1^(CE Controlled, OE is HIGH or LOW) ^{(1 )}
t WC
ADDRESS
CE
WE
DOUT
DIN
VALID ADDRESS
t SA
t SCE
t HA
DATA UNDEFINED
t AW
t PWE1
t PWE2
t HZWE
HIGH-Z
t LZWE
t SD
t HD
DATAIN VALID
6
Integrated Circuit Solution Inc.
SR004-0D