IC41C82002S Datasheet, PDF (6/19 Pages) Integrated Circuit Solution Inc – 2Mx8 bit Dynamic RAM with EDO Page Mode

IC41C82002S
IC41LV82002S
ELECTRICAL CHARACTERISTICS⁽¹⁾
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter
IIL
Input Leakage Current
IIO
Output Leakage Current
VOH
Output High Voltage Level
VOL
Output Low Voltage Level
ICC1
Standby Current: TTL
Test Condition
Any input 0V ≤ VIN ≤ Vcc
Other inputs not under test = 0V
Output is disabled (Hi-Z)
0V ≤ VOUT ≤ Vcc
IOH = –5.0 mA with VCC=5V
IOH = –2.0 mA with VCC=3.3V
IOL = 4.2 mA with VCC=5V
IOL = 2 mA with VCC=3.3V
RAS, CAS ≥ VIH
ICC2
Standby Current: CMOS
RAS, CAS ≥ VCC – 0.2V
ICC3
Operating Current:
RAS, CAS,
Random Read/Write^(2,3,4)
Address Cycling, tRC = tRC (min.)
Average Power Supply Current
ICC4
Operating Current:
RAS = VIL, CAS Cycling,
EDO Page Mode^(2,3,4)
tRC = tRC (min.)
Average Power Supply Current
ICC5
Refresh Current:
RAS Cycling, CAS ≥ VIH
RAS-Only^(2,3)
tRC = tRC (min.)
Average Power Supply Current
ICC6
Refresh Current:
RAS, CAS Cycling
CBR^(2,3,5)
tRC = tRC (min.)
Average Power Supply Current
ICCS
Self Refresh Current
Self Refresh Mode
Speed Min. Max. Unit
–5
5
µA
–5
5
µA
2.4 —
V
—
0.4
V
5V —
3.3V —
5V —
3.3V —
-50 —
-60 —
2 mA
0.5
1
mA
0.5
120 mA
110
-50 —
-60 —
90 mA
80
-50 — 120 mA
-60 — 110
-50 — 120 mA
-60 — 110
5V — 300 µA
3.3V — 300 µA
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
6
Integrated Circuit Solution Inc.
DR022-0A 08/20/2001