IC41C4400x Datasheet, PDF (2/20 Pages) Integrated Circuit Solution Inc – 4Mx4 bit Dynamic RAM with EDO Page Mode

IC41C4400x and IC41LV4400x Series
4M x 4 (16-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
FEATURES
• Extended Data-Out (EDO) Page Mode
access cycle
• TTL compatible inputs and outputs
• Refresh Interval:
-- 2,048 cycles/32 ms
-- 4,096 cycles/64 ms
• Refresh Mode: RAS-Only,
CAS-before-RAS (CBR), and Hidden
• JEDEC standard pinout
• Single power supply:
5V ± 10% or 3.3V ± 10%
• Byte Write and Byte Read operation via
two CAS
PRODUCT SERIES OVERVIEW
Part No.
Refresh
Voltage
IS41C44002
2K
5V ± 10%
IS41C44004
4K
5V ± 10%
IS41LV44002
2K
3.3V ± 10%
IS41LV44004
4K
3.3V ± 10%
DESCRIPTION
The ICSI 4400 Series is a 4,194,304 x 4-bit high-performance
CMOS Dynamic Random Access Memory. These devices
offer an accelerated cycle access called EDO Page Mode.
EDO Page Mode allows 2,048 or 4096 random accesses within
a single row with access cycle time as short as 20 ns per 4-bit
word.
These features make the 4400 Series ideally suited for high-
bandwidth graphics, digital signal processing, high-performance
computing systems, and peripheral applications.
The 4400 Series is packaged in a 24-pin 300mil SOJ and a 24
pin TSOP-2
KEY TIMING PARAMETERS
Parameter
RAS Access Time (tRAC)
CAS Access Time (tCAC)
Column Address Access Time (tAA)
EDO Page Mode Cycle Time (tPC)
Read/Write Cycle Time (tRC)
-50 -60 Unit
50 60 ns
13 15 ns
25 30 ns
20 25 ns
84 104 ns
PIN CONFIGURATION
24 Pin SOJ, TSOP-2
VCC 1
I/O0 2
I/O1 3
WE 4
RAS 5
*A11(NC) 6
24 GND
23 I/O3
22 I/O2
21 CAS
20 OE
19 A9
A10 7
A0 8
A1 9
A2 10
A3 11
VCC 12
18 A8
17 A7
16 A6
15 A5
14 A4
13 GND
PIN DESCRIPTIONS
A0-A11 Address Inputs (4K Refresh)
A0-A10 Address Inputs (2K Refresh)
I/O0-3
WE
OE
RAS
CAS
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Column Address Strobe
Vcc
Power
GND Ground
NC
No Connection
* A11 is NC for 2K Refresh devices.
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
DR007-0B 10/17/2002