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IC61SP12832 Datasheet, PDF (10/16 Pages) Integrated Circuit Solution Inc – 128K x 32 Pipelined SyncBurst SRAM | |||
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IC61SP12832
IC61SP12836
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol Parameter
-166
-150
-133
-117
-5
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
fMAX Clock Frequency
â 166 â 150 â 133 â 117 â 100 MHz
tKC
Cycle Time
6â
6.7 â
7.5 â
8.5 â
10 â
ns
tKH
Clock High Time
2.4 â
2.6 â
2.8 â
3.4 â
4â
ns
tKL
Clock Low Time
2.4 â
2.6 â
2.8 â
3.4 â
4â
ns
tKQ
Clock Access Time
â 3.5
â 3.8
â4
â4
â5
ns
tKQX(1) Clock High to Output Invalid
1.5 â
1.5 â
1.5 â
1.5 â
2.5 â
ns
tKQLZ(1,2) Clock High to Output Low-Z
0â
0â
0â
0â
0â
ns
tKQHZ(1,2) Clock High to Output High-Z
1.5 6
1.5 6.7
1.5 7.5
1.5 8.5
1.5 10
ns
tOEQ Output Enable to Output Valid â 3.5
â 3.5
â 3.8
â4
â5
ns
tOEQX(1) Output Disable to Output Invalid 0
â
0â
0â
0â
0â
ns
tOELZ(1,2) Output Enable to Output Low-Z 0
â
0â
0â
0â
0â
ns
tOEHZ(1,2) Output Disable to Output High-Z 2 3.5
2 3.5
2 3.8
24
2
5
ns
tAS
Address Setup Time
1.5 â
1.5 â
1.5 â
1.5 â
1.5 â
ns
tSS
Address Status Setup Time
1.5 â
1.5 â
1.5 â
1.5 â
1.5 â
ns
tWS
Write Setup Time
1.5 â
1.5 â
1.5 â
1.5 â
1.5 â
ns
tCES Chip Enable Setup Time
1.5 â
1.5 â
1.5 â
1.5 â
1.5 â
ns
tAVS Address Advance Setup Time 1.5 â
1.5 â
1.5 â
1.5 â
1.5 â
ns
tAH
Address Hold Time
0.5 â
0.5 â
0.5 â
0.5 â
0.5 â
ns
tSH
Address Status Hold Time
0.5 â
0.5 â
0.5 â
0.5 â
0.5 â
ns
tWH Write Hold Time
0.5 â
0.5 â
0.5 â
0.5 â
0.5 â
ns
tCEH Chip Enable Hold Time
0.5 â
0.5 â
0.5 â
0.5 â
0.5 â
ns
tAVH Address Advance Hold Time
0.5 â
0.5 â
0.5 â
0.5 â
0.5 â
ns
Note:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
10
Integrated Circuit Solution Inc.
SSR019-0A 09/17/2001
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