IC61SF25632T Datasheet, PDF (10/19 Pages) Integrated Circuit Solution Inc – 8Mb SyncBurst Flow through SRAM

IC61SF25632T/D IC61SF25636T/D
IC61SF51218T/D
Mode Pin Functions
Mode Name
Pin Name
State
Function
Burst Order Control
Power Down Control
Output Drive Control
MODE
ZZ
XQ
L
H or NC
L or NC
H
L
H
Linear Burst
Interleaved Burst
Active
Standby
High Drive (Low Impedance)
Low Drive (High Impedance)
Note:
There are pull-up devices on the MODE, XQ, SCD, and a pull down device on the ZZ pin, so those input pins can be unconnected
and the chip will operate in the default states as specified in the above table.
TRUTH TABLE
Operation
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Address
Used CE CE2 CE2
None H X X
None L X H
None L L X
None L X H
None L L X
External L H L
External L H L
External L H L
Next X X X
Next X X X
Next H X X
Next H X X
Next X X X
Next H X X
Current X X X
Current X X X
Current H X X
Current H X X
Current X X X
Current H X X
PARTIAL TRUTH TABLE
Function
GW BWE BWa BWb BWc BWd
Read
H H XXX X
Read
H
L
HHH H
Write Byte 1
H
L
L HH H
Write All Bytes
H
L
LLL L
Write All Bytes
L
X XXX X
ADSP
X
L
L
H
H
L
H
H
H
H
X
X
H
X
H
H
X
X
H
X
ADSC
L
X
X
L
L
X
L
L
H
H
H
H
H
H
H
H
H
H
H
H
ADV
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
WRITE
X
X
X
X
X
X
Read
Write
Read
Read
Read
Read
Write
Write
Read
Read
Read
Read
Write
Write
OE DQ
X High-Z
X High-Z
X High-Z
X High-Z
X High-Z
XQ
XQ
XD
LQ
H High-Z
LQ
H High-Z
XD
XD
LQ
H High-Z
LQ
H High-Z
XD
XD
10
Integrated Circuit Solution Inc.
SSR020-0A 9/03/2002