X24C02 Datasheet, PDF (7/16 Pages) Xicor Inc. – Serial E2PROM

X24C02
Current Address Read
Internally the X24C02 contains an address counter that
maintains the address of the last word accessed,
incremented by one. Therefore, if the last access (either
a read or write) was to address n, the next read operation
would access data from address n + 1. Upon receipt of the
slave address with the R/W bit set to one, the
X24C02 issues an acknowledge and transmits the eight bit
word during the next eight clock cycles. The master
terminates this transmission by issuing a stop condition,
omitting the ninth clock cycle acknowledge. Refer to
Figure 7 for the sequence of address, acknowledge and
data transfer.
Figure 7. Current Address Read
Random Read
Random read operations allow the master to access any
memory location in a random manner. Prior to issuing
the slave address with the R/W bit set to one, the master
must first perform a “dummy” write operation. The master
ter issues the start condition, and the slave address
followed by the word address it is to read. After the word
address acknowledge, the master immediately reissues
the start condition and the slave address with the R/W bit
set to one. This will be followed by an acknowledge from
the X24C02 and then by the eight bit word. The master
terminates this transmission by issuing a stop condition,
omitting the ninth clock cycle acknowledge. Refer to
Figure 8 for the address, acknowledge and data transfer
sequence.
S
T
BUS ACTIVITY: ^A
MASTER
R
T
SLAVE
ADDRESS
S
DATA
T
O
P
SDA LINE
S
P
A
BUS ACTIVITY:
C
X24C02
K
3838 FHD F13
Figure 8. Random Read
S
T
BUS ACTIVITY: ^A
MASTER
R
T
SLAVE
ADDRESS
WORD
ADDRESS n
S
T
A
R
SLAVE
ADDRESS
T
DATA n
SDA LINE
S
S
BUS ACTIVITY:
X24C02
A
A
A
C
C
C
K
K
K
S
T
O
P
P
3838 FHD F14
7