X25650 Datasheet, PDF (5/14 Pages) Xicor Inc. – 5MHz SPI Serial E 2 PROM with Block Lock TM Protection

X25650
Hold Operation
The HOLD input should be HIGH (at V_IH) under normal
operation. If a data transfer is to be interrupted HOLD
can be pulled LOW to suspend the transfer until it can
be resumed. The only restriction is the SCK input must
be LOW when HOLD is first pulled LOW and SCK
must also be LOW when HOLD is released.
The HOLD input may be tied HIGH either directly to
V_CC or tied to V_CC through a resistor.
Figure 1. Read E²PROM Array Operation Sequence
Operational Notes
The X25650 powers-up in the following state:
• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
• SO pin is high impedance.
• The “write enable” latch is reset.
Data Protection
The following circuitry has been included to prevent in-
advertent writes:
• The “write enable” latch is reset upon power-up.
• A WREN instruction must be issued to set the “write
enable” latch.
• CS must come HIGH at the proper clock count in or-
der to start a write cycle.
CS
SCK
SI
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23 24 25 26 27 28 29 30
INSTRUCTION
16 BIT ADDRESS
15 14 13
3 210
HIGH IMPEDANCE
SO
Figure 2. Read Status Register Operation Sequence
76
MSB
DATA OUT
5432 10
7037 FRM F03
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
INSTRUCTION
SI
HIGH IMPEDANCE
SO
76
MSB
DATA OUT
5432
10
7037 FRM F04
5