X25170 Datasheet, PDF (5/15 Pages) IC MICROSYSTEMS – SPI Serial E 2 PROM with Block Lock ™ Protection

X25170
Figure 1. Read E²PROM Array Operation Sequence
CS
SCK
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23 24 25 26 27 28 29 30
Instruction
SI
16 Bit Address
15 14 13
3 210
High Impedance
SO
Figure 2. Read Status Register Operation Sequence
CS
Data Out
7 65432 10
MSB
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Instruction
SI
High Impedance
SO
Data Out
76543210
MSB
Write Sequence
Prior to any attempt to write data into the X25170, the
“write enable” latch must first be set by issuing the
WREN instruction (See Figure 3). CS is first taken
LOW, then the WREN instruction is clocked into the
X25170. After all eight bits of the instruction are trans-
mitted, CS must then be taken HIGH. If the user con-
tinues the write operation without taking CS HIGH after
issuing the WREN instruction, the write operation will
be ignored.
To write data to the E²PROM memory array, the user
issues the WRITE instruction, followed by the address
and then the data to be written. This is minimally a
thirty-two clock operation. CS must go LOW and
remain LOW for the duration of the operation. The host
may continue to write up to 32 bytes of data to the
X25170. The only restriction is the 32 bytes must reside
on the same page. If the address counter reaches the
end of the page and the clock continues, the counter will
“roll over” to the first address of the page and overwrite
any data that may have been written.
Characteristics subject to change without notice. 5 of 15