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IC-LNG Datasheet, PDF (9/25 Pages) IC-Haus GmbH – 16-BIT OPTO ENCODER WITH SPI AND SERIAL /PARALLEL OUTPUTS | |||
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iC-LNG 16-BIT OPTO ENCODER preliminary
WITH SPI AND SERIAL / PARALLEL OUTPUTS
Rev A1, Page 9/25
ELECTRICAL CHARACTERISTICS
Operating conditions: VDDA = 4 V to 5.5 V, VDD = 3 V to 5.5 V, GNDA = GND, Tj = -40°C to 125°C, unless otherwise speciï¬ed.
Item Symbol Parameter
No.
Conditions
Min. Typ. Max.
SPI Interface SCK, CS, MISO, MOSI
901 ï¬n()
Permissible Input Frequency at
10
SCK
902 Vt()hi
Threshold Voltage hi at SCK, CS,
2
MOSI
903 Vt()lo
Threshold Voltage lo at SCK, CS,
0.8
MOSI
904 Vt()hys Hysteresis at SCK, CS, MOSI Vt() = Vt()hi - Vt()lo
40 100
905 Ipu()
Pull-Up Current at SCK, MOSI
V() = 0 V to VDD - 1 V
VDD = 3 V to 4 V
VDD = 4 V to 5.5 V
-65 -25
-5
-120 -60 -10
906 Vpu()
Pull-Up Voltage at SCK, MOSI Vpu() = VDD - V(),
400
VDD = 3 V to 4 V, I() = -3 µA
VDD = 4 V to 5.5 V, I() = -5 µA
907 Ipd()
Pull-Down Current at CS
V() = 1 V . . . VDD
VDD = 3 V to 4 V
VDD = 4 V to 5.5 V
5
25
80
8
60 150
908 Vpd()
Pull-Down Voltage at CS
VDD = 3 V to 4 V, I() = 3 µA
400
VDD = 4 V to 5.5 V, I() = 5 µA
909 tCO
Propagation Delay: MISO hi
see Figure 2
30
after Falling Edge CS
910 tSO
Propagation Delay: MISO Stable see Figure 2
30
after Clock Edge SCK
Shift Register CLK, NSL, DOUT, DIN
A01 ï¬n()
Permissible Input Frequency at
16
CLK
A02 tNO
Propagation Delay: DOUT
see Figure 3
20
after Falling Edge NSL
A03 tCO
Propagation Delay: DOUT stable see Figure 3
20
after Clock Edge CLK
A04 Vt()hi
Threshold Voltage hi at CLK,
2
NSL, DIN
A05 Vt()lo
Threshold Voltage lo at CLK,
0.8
NSL, DIN
A06 Vt()hys Hysteresis at CLK, NSL, DIN Vt() = Vt()hi - Vt()lo
40 100
A07 Ipu()
Pull-Up-Current at CLK, NSL
V() = 0 V to VDD - 1 V
VDD = 3 V to 4 V
VDD = 4 V to 5.5 V
-65 -25
-5
-120 -60 -10
A08 Vpu()
Pull-Up-Voltage at CLK, NSL Vpu() = VDD-V(),
400
VDD = 3 V to 4 V, I() = -3 µA
VDD = 4 V to 5.5 V, I() = -5 µA
A09 Ipd()
Pull-Down Current at DIN
V() = 1 V to VDD
VDD = 3 V to 4 V
VDD = 4 V 5.5 V
5
25
80
8
60 150
A10 Vpd()
Pull-Down-Voltage at DIN
VDD = 3 V to 4 V, I() = 3 µA
400
VDD = 4 V to 5.5 V, I() = 5 µA
Parallel Output Bit 0 to Bit 13 (Parameter EPG = 0x1)
B01 Vs()hi
Saturation Voltage hi
Vs()hi = VDD - V()
400
VDD = 3 V to 4 V, I() = 2.5 mA,
VDD = 4 V to 5.5 V, I() = 3.5 mA
B02 Isc()hi
Short-Circuit Current hi
-100
-4
B03 Vs()lo
Saturation Voltage lo
VDD = 3 V to 4 V, I() = 2.5 mA,
400
VDD = 4 V to 5.5 V, I() = 3.5 mA
B04 Isc()lo
Short-Circuit Current lo
4
100
B05 tr()
Rise Time
CL = 30 pF, V(): 10% â 90% VDD
30
B06 tf()
Fall Time
CL = 30 pF, V(): 90% â 10% VDD
30
Unit
MHz
V
V
mV
µA
µA
mV
µA
µA
mV
ns
ns
MHz
ns
ns
V
V
mV
µA
µA
mV
µA
µA
mV
mV
mA
mV
mA
ns
ns
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