IC-OC Datasheet, PDF (7/9 Pages) IC-Haus GmbH – INTEGRATING LIGHT-VOLTAGE CONVERTER

iC-OC
INTEGRATING LIGHT-VOLTAGE CONVERTER
DESCRIPTION OF FUNCTIONS
Rev D1, Page 7/9
iC-OC is an integrating light-voltage converter with two
separate photodiodes and two integrators. The inte-
gration time starts when the supply voltage is applied.
To obtain a specified integration time a hi pulse must
first be available at the digital input DIN and clocked by
the device. This process sequentially resets the inte-
grators to their initial value and restarts the integration
time with the next clock pulse.
Flip-flops Q1 to Q3 sequentially accept the signal at
DIN with the positive CLK edge. Flip-flop Q4, which
controls the DOUT output signal, reacts to the nega-
tive CLK edge. The switching states in the IC always
remain for the duration of a clock cycle. The process
depicted in Fig. 2 is initiated when a hi pulse is applied
to DIN.
During the first clock cycle integrator 1 is switched to
the analogue output AOUT (switch SOUT1 closes).
AOUT initially supplies a voltage value which cannot
be reproduced as the integration time is unknown. The
second clock cycle switches the analogue output from
integrator 1 to integrator 2 (SOUT1 opens, SOUT2
closes). A non-reproducible voltage value is again
present at AOUT (see above). At the same time the
integration capacity of integrator 1 is short-circuited by
switch SC1 (reset).
Flip-flop Q4 is set in the second clock cycle with the
negative clock edge (DOUT1) and thus the DIN signal
for the next device in the chain is produced.
During the third clock cycle integrator 2 is discon-
nected from AOUT (SOUT2 opens) and reset (SC2
closes). Simultaneously, the integration time for inte-
grator 1 starts anew (SC1 opens). If several iC-OCs
are connected in a chain, then the hi signal from DOUT
is shifted into the first flip-flop of the next device with
the third clock cycle. During the fourth clock cycle
switch SC2 opens and starts the integration time for
integrator 2.
APPLICATIONS INFORMATION
Only when the DOUT2 output has a hi level can the
next hi signal be applied to DIN1. The first hi signal
clocked by the device implements a sequential reset of
the integrators, followed by the integration time starting
in sequence. The second hi signal shifted through the
register determines the end of the integration time and
restarts the integration time after a reset. The integra-
tors can be read out with the aid of a sample and hold
circuit, as the device itself has no hold mode. Besides
the clock a periodic signal at DIN is also necessary for
the continuous operation of the device.
With operation of the device at low level illumination
the output voltage V(AOUT) decreases by V0(AOUT).
When calibrating, this drop in voltage must be deter-
mined for each of the photosensors.
VDD
AOUT
DIN1
CLK
GND AOUT VDD
GND AOUT VDD
iC−OC
DIN
CLK
DOUT
iC−OC
DIN
CLK DOUT
DOUT1= DIN2
DOUT2
Figure 5: Example of a chain connection for two de-
vices