IC-OC Datasheet, PDF (4/9 Pages) IC-Haus GmbH – INTEGRATING LIGHT-VOLTAGE CONVERTER

iC-OC
INTEGRATING LIGHT-VOLTAGE CONVERTER
Rev D1, Page 4/9
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 5 V ±10 %, RL(VDD/AOUT) = 1 kΩ, Tj = 0...85 °C unless otherwise noted
Item Symbol Parameter
No.
Conditions
Min. Typ. Max.
Total Device
001 VDD
Permissible Supply Voltage
Range
4.5
5.5
002 I(VDD) Supply Current in VDD
100
700
003 Vc()hi
Clamp Voltage hi at DIN, CLK, Vc()hi = V() − VDD, I() = 10 mA,
DOUT, AOUT
other pins open
0.3
1.5
004 Vc()lo
Clamp Voltage lo at DIN, CLK, I() = -10 mA, other pins open
DOUT, AOUT
-1.5
-0.3
005 Aph()
Radiant Sensitive Area
ca. 0.97 x 0.47
006 λar
Spectral Application Range
S(λar) = 0.25 x S(λ)max
300
950
Analogue Output AOUT
201 V0()
Output Voltage at no illuminance V0() = VDD − V(AOUT)max,
AOUT active (* see below)
0.7
1.4
202 ∆Vd()
Variation of Output Voltage at no ∆Vd() = V(AOUT)t1 − V(AOUT)t2,
illuminance
∆t = t2 − t1 = 1 ms
-10
10
203 Vs()
Saturation Voltage
Tenfold illuminance
VDD = 4.5 V
1.4
VDD = 5 V
1.45
VDD = 5.5 V
1.5
204 ∆V()
Repeatability (standard deviation 20 measurements at constant LED illuminance,
15
at repeated measurement)
Vav(AOUT) ≈ 2.91 V, ∆t = 25 µs
205 Vlin()
Output Voltage Linearity Range Vlin() = VDD − V0() − V(AOUT)
1.7
206 K
207 ∆klin
Transfer Factor
output voltage vs. light power
Transfer Factor Deviation within
linearity range
BMST assembly incl. sealing;
λ_LED = 628 nm, ∆λ = ±23 nm
λ_LED = 880 nm, ∆λ = ±40 nm
0.22 0.27 0.32
0.13 0.16 0.19
-5
5
208 I()
Leakage Current
V(AOUT) = 0...VDD,
-2
2
AOUT high impedance (* see below)
Shift-Register DIN, CLK, DOUT
301 Vt()hi
Threshold Voltage hi at DIN, CLK
2.2
302 Vt()lo
Threshold Voltage lo at DIN, CLK
0.8
303 Vt()hys Hysteresis at DIN, CLK
Vt()hys = Vt()hi − Vt()lo
250
1300
304 Ii()
Input Current in DIN, CLK
V() = 0...VDD
-1
1
305 f()
Permissible Frequency at CLK
10
306 tw()hi
Permis. Pulse Width hi at CLK
20
307 tw()lo
Permis. Pulse Width lo at CLK
20
308 tplh
Propagation Delay: CLK hi → lo CL(DOUT) = 50 pF (see Fig. 2)
40
until DOUT lo → hi
309 tphl
Propagation Delay: CLK hi → lo CL(DOUT) = 50 pF (see Fig. 2)
40
until DOUT hi → lo
310 tpon
Propagation Delay: CLK lo → hi CL(VDD/AOUT) = 1 nF (see Fig. 2)
800
until AOUT active
311 tpoff
Propagation Delay: CLK lo → hi CL(VDD/AOUT) = 1 nF (see Fig. 2)
100
until AOUT high impedance
312 Vs()hi
Saturation Voltage hi at DOUT Vs()hi = VDD − V(), I() = -1 mA
0.4
313 Vs()lo
Saturation Voltage lo at DOUT I() = 1 mA
0.4
Low Voltage Detection
401 VDDon Turn-on Threshold VDD
Increasing voltage at VDD
2.1
3.8
402 VDDoff Undervoltage Threshold VDD Decreasing voltage at VDD
1.0
2.1
403 VDDhys Hysteresis
VDDhys = VDDon − VDDoff
0.5
2
(*) _{AOUT active: SOUT1 or SOUT2 closed; AOUT high impedance: SOUT1 and SOUT2 open.}
Unit
V
µA
V
V
mm²
nm
V
mV
V
V
V
mV
V
V/pWS
V/pWS
%
µA
V
V
mV
µA
MHz
ns
ns
ns
ns
ns
ns
V
V
V
V
V