IC-NQC_13 Datasheet, PDF (7/30 Pages) IC-Haus GmbH – Sin/D CONVERTER WITH SIGNAL CALIBRATION

iC-NQC
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Rev D3, Page 7/30
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDDA = VDD = 5 V ±10 %, Tj = -40 ... 125 °C, unless otherwise stated.
Item Symbol Parameter
No.
Conditions
Zero Signal Enable Inputs PZERO, NZERO
B01 Vos()
Input Offset Voltage
V() = Vcm()
B02 Iin()
Input Current
V() = 0 V ... VDDA
B03 Vcm()
Common-Mode Input Voltage
Range
B04 Vdm()
Differential Input Voltage Range
Incremental Outputs A, B, Z and I/O Interface Output SLO
D01 Vs()hi
Saturation Voltage hi
Vs()hi = VDD - V(); I() = -4 mA
D02 Vs()lo
Saturation Voltage lo
I() = 4 mA
D03 tr()
Rise Time
CL() = 50 pF
D04 tf()
Fall Time
CL() = 50 pF
D05 RL()
Permissible Load at A, B
TMA = 1 (calibration mode)
I/O Interface Inputs MA, SLI
E01 Vt()hi
Threshold Voltage hi
E02 Vt()lo
Threshold Voltage lo
E03 Vt()hys Hysteresis
Vt()hys = Vt()hi - Vt()lo
E04 Ipu(MA) Pull-up Current in MA
V() = 0 ... VDD - 1 V
E05 Ipd(SLI) Pull-down Current in SLI
V() = 1 ... VDD
E06 fclk(MA) Permissible MA Clock Frequency SSI protocol
BiSS protocol
E07 tp(MA-
SLO)
Propagation Delay:
MA edge vs. SLO output
RL(SLO) ≥ 1 kΩ
E08 tbusy_s
Processing Time Single-Cycle
Data (delay of start bit)
E09 tbusy_r
Processing Time Register Ac-
cess (delay of start bit)
with read access to EEPROM
E10 tidle
Interface Blocking Time
powering up with no EEPROM
E11 t_tos
Timeout
TIMO = 0, TOA =0
EEPROM Interface Inputs SDA and Error Input NERR
F01 Vt()hi
Threshold Voltage hi
F02 Vt()lo
Threshold Voltage lo
F03 Vt()hys Hysteresis
Vt()hys = Vt()hi - Vt()lo
F04 tbusy()cfg Duration of Startup Configuration error free EEPROM access
EEPROM Interface Outputs SDA, SCL and Error Output NERR
G01 f()
Write/Read Clock at SCL
G02 Vs()lo
Saturation Voltage lo
I() = 4 mA
G03 Ipu()
Pull-up Current
V() = 0 ... VDD - 1 V
G04 ft()
Fall Time
CL() = 50 pF
G05 tmin()lo
G06 Tpwm()
Min. Duration Of Error Indication
at NERR (lo signal)
Cycle Duration Of Error Indica-
tion at NERR
MA = hi, no BiSS access, amplitude or frequeny
error
fosc() subdivided 2²²
G07 t()lo
Duty Cycle Of Error Indication at signal duration low to high;
NERR
AERR = 0 (amplitude error)
FERR = 0 (frequency error)
G08 RL()
Permissible Load at SDA, SCL TMA = 1 (calibration mode)
Min.
-20
-50
1.4
0
1
0.8
300
-240
20
10
0.8
300
-600
10
1
Unit
Typ. Max.
20
mV
50
nA
VDDA- V
1.5
VDDA V
0.4
V
0.4
V
60
ns
60
ns
MΩ
2
V
V
mV
-120 -25
µA
120 300 µA
4
MHz
10 MHz
50
ns
0
µs
2
ms
1
1.5
ms
20
µs
2
V
V
mV
5
7
ms
20 100 kHz
0.45
V
-300 -75
µA
60
ns
ms
60.7
ms
75
%
50
%
MΩ