IC-LA Datasheet, PDF (7/8 Pages) IC-Haus GmbH – 64X1 LINEAR IMAGE SENSOR

iC-LA
64X1 LINEAR IMAGE SENSOR
Rev A3, Page 7/8
DESCRIPTION OF FUNCTIONS
In the following description it is assumed that DNU is set to lo. If a hi pulse is available at DIN, integration
operation of iC-LA is initiated with the next rising edge of the CLK clock signal.
During the first clock cycle all integration capacitors are discharged with the falling edge at CLK. In this clock
cycle the chip temperature is output at AOUT. In the second clock cycle all integration capacitors are precharged
to VCMIN; with the falling edge of the clock signal all 64 pixels start to be integrated.
In this clock cycle all track-and-hold circuits are in hold mode; the voltage of the pixel 0 track-and-hold capacitor
is switched to AOUT. This voltage is initially unknown as the track-and-hold capacitors of a pixel have not been
reset. With the rising edge of the third clock cycle pixel 0 changes into track mode. With this, the voltage of the
pixel 1 track-and-hold capacitor is switched to AOUT, which again is unknown. With the rising edge of the next
clock cycle pixel 1 changes into track mode and the voltage of the track-and hold-capacitor from pixel 2 is
switched to AOUT.
At the 66^th clock cycle the temperature is available at AOUT, completing the initialization of the device (initial run).
The stored integration voltages from the initial run are available at AOUT during the next run.
If a new hi pulse is available at DIN, a complete new integration cycle starts (run 1) and the sequence of the
device repeats. In the first clock cycle of run 1 all track-and-hold circuits again switch into hold mode; all
integration capacitors are discharged. During the second clock cycle all integration capacitors are recharged to
VCMIN and the integration process restarts.
Between this and the 66^th clock cycle the pixel voltages stored in the previous integration cycle in the track-and-
hold capacitors are present at AOUT for the duration of one cycle.
It again takes 66 clock cycles for the voltages from all of the switch-and-hold capacitors to be read out. The last
clock cycle again outputs the chip temperature and completes the run. Continuous operation of the device is
obtained when DIN is again given a hi signal after a run has been completed by the 66^th clock cycle.
Fig. 4: timing diagram