IC149_13 Datasheet, PDF (6/8 Pages) IC-Haus GmbH – PROGRAMMABLE ns-PULSE GENERATOR

iC149
preliminary
PROGRAMMABLE ns-PULSE GENERATOR
SAMPLE PULSES
Rev A2, Page 6/8
Figure 7: In pulse mode (S2 left hand position)
the rising edge of the trigger signal and
the LVDS appear simultaneously. The
TTL/CMOS has an approx. 1 ns delay.
Figure 8: In the symmetrical mode (S2 right hand
position) the rising edge of the trigger sig-
nal has an approx. 20 ns delay with refer-
ence to the output signals.
Figure 9: Maximum pulse width at switch setting
"FF"
Figure 10: Minimum pulse width at switch setting
"0B"