IC-VRV Datasheet, PDF (5/12 Pages) IC-Haus GmbH – BIDIRECTIONAL μP INTERFACE TO 24V

iC-VRV
BIDIRECTIONAL µP INTERFACE TO 24V
Rev A2, Page 5/12
Signal changes which would be relevant for an interrupt generation could occur in the read-out phase following
an interrupt message. These signal changes are lost when the interrupt register is deleted. As an alternative, the
read-out of the interrupt register is possible (functional selection: read IR inputs). The registers can then be reset
separately by blocking the IR enable for each reporting stage singly and then releasing it (functional selection:
IR enable).
Filter periods
The input comparator of each I/O stage switches the counting direction of a 3 bit counter. The counter output Q
does not change until the final status is reached (to high for high level at IOx, to low for low level at IOx if
constantly applied during the filter period).
The counter is clocked externally (pin CLK); the divisor for the clock frequency can be programmed separately
for both nibbles. A low signal at reset input RESN resets the counters to the value 3. Due to the digital hysteresis,
the change of an input signal is therefore not recognized until the selected filter period has elapsed.
Pulse enable and pulse times
The flashing or pulsing function can be switched on separately for each I/O stage with output function. The
programming of the divisors for the flashing frequency input BLFQ (control word 1, bits 0,1 and 4,5) is conducted
for each nibble. The clock signal at BLFQ is transfered with the slope of CLK (synchronized). For this reason the
clock frequency for CLK must be higher than the clock frequency for BLFQ, e. g. 2 MHz for CLK and 50 Hz for
BLFQ.
Control Word 1
higher nibble
lower nibble
Bit
7
6
5
4
3
2
1
0
Name
FH0
FH1
PH0
PH1
FL0
FL1
PL0
PL1
Control Word 1 (lower nibble)
Filtering Time
Bit 3
FLO
Bit 2
FL1
0
0
14.5 * CLK
1
0
896.5 * CLK
0
1
3584.5 * CLK
1
1
7168.5 * CLK
± 1 * CLK
± 64 * CLK
± 256 * CLK
± 512 * CLK
Flashing Pulse Duration
Bit 1
PLO
Bit 0
PL1
0
0
BLFQ
1
0
BLFQ * 2
0
1
BLFQ * 4
1
1
BLFQ * 16
Control Word 1 (higher nibble)
Filtering Time
Bit 7 Bit 6
FHO FH1
0
0
14.5 * CLK
± 1 * CLK
1
0
896.5 * CLK ± 64 * CLK
0
1
3584.5 * CLK ± 256 * CLK
1
1
7168.5 * CLK ± 512 * CLK
Flashing Pulse Duration
Bit 5 Bit 4
PHO PH1
0
0
BLFQ
1
0
BLFQ * 2
0
1
BLFQ * 4
1
1
BLFQ * 16