IC-VRV Datasheet, PDF (4/12 Pages) IC-Haus GmbH – BIDIRECTIONAL μP INTERFACE TO 24V

iC-VRV
BIDIRECTIONAL µP INTERFACE TO 24V
PROGRAMMING
Rev A2, Page 4/12
Selection of functions
Data Word D7..D0
higher nibble
lower nibble
Selected I/O Stage function:
Address
A1 A0
Write
Input
Read
Output
Write
Read
Write
Input
Read
0
0
Test Pattern IR Inputs Outputs
Outputs
Test Pattern IR Inputs
0
1
IR Enable IR Enable Pulse Enable Pulse Enable IR Enable IR Enable
Control
1
0
Word 2
Inputs
Control
Word 2
Feedback
I/O Stages
Control
Word 2
Inputs
Control
1
1
Word 1
Control
Word 1
Control
Word 1
Control
Word 1
Control
Word 1
Control
Word 1
Write
Output
Read
Outputs
Outputs
Pulse Enable Pulse Enable
Control
Word 2
Feedback
I/O Stages
Control
Word 1
Control
Word 1
Reading the inputs or the output feedback (IO7..0 to D7..0)
I/O stage with input function: A high level at IOx generates a high signal at Dx (selection of functions:
read inputs) during the course of the digital hysteresis.
I/O stage with output function: A high level at IOx generates a low signal at Dx (selection of functions:
read feedback of the outputs).
The inversion while reading back the outputs (I/O stage with output function) occurs so that the same signal is
applied to Dx as was programmed for switching the output stage on or off, for example: switching on the final
stage with Dx = high results in low level at IOx. After the digital hysteresis ends, Q becomes low, the
microprocessor interface inverts this message and a high signal can be read back via Dx. The microprocessor
can check the output state in this manner.
Test
The test circuit consists of registers which can be set via the microprocessor interface (test pattern). Its content
is applied via constantly active OR gates to the counting direction inputs UP/DOWN (D7..0 to UP/DOWN7..0).
In response to a reset (low signal at RESN) the registers are set to low; as a result, there is no effect on the
UP/DOWN inputs.
In the test mode (control word 2, bit 2 and 6 at high) the comparators of the I/O stages are switched off and only
the test registers continue to operate the UP/DOWN inputs. Any desired input signals can be entered to test all
digital functions; the microprocessor can also conduct a system test in this manner.
Interrupt enable
The interrupt generation can be activated separately for every I/O stage with input function. The interrupt enable
is programmed via the data word DO..7 (function selection IR enable: 1 = stage relevant, 0 = stage not relevant).
If a signal change is recognized for an I/O stage with input function - after the digital hysteresis due to change
at Qx - and if this stage is enabled for interrupt generation, this is indicated with INTN = low. The interrupt
message as well as the interrupt register which shows the stages with signal changes are reset via control word
2 (writing bit 0 = 1 is sufficient; bit 0 = 0 is set by the chip automatically).