HYMD564M646AL6-D43 Datasheet, PDF (9/17 Pages) Hynix Semiconductor – Unbuffered DDR SO-DIMM

HYMD564M646A(L)6-D43/D4/J
DC CHARACTERISTICS II (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Test Condition
Speed
D43 D4 J
Unit Note
Operating Current
IDD0
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing
twice per clock cycle ; address and control inputs
changing once per clock cycle
640
600 mA
Operating Current
One bank; Active - Read - Precharge; Burst Length =2;
IDD1 tRC=tRC(min); tCK=tCK(min); address and control
840
inputs changing once per clock cycle
760 mA
Precharge Power
Down Standby Current
IDD2P
All banks idle; Power down mode; CKE=Low, tCK=
tCK(min)
80
mA
Idle Standby Current
IDD2N Vin>=Vih(min) or Vin=<Vil(max) for DQ, DQS and DM
180
mA
Idle Standby Current
IDD2F
/CS=High, All banks idle; tCK=tCK(min); CKE= High;
address and control inputs changing once per clock
cycle. VIN=VREF for DQ, DQS and DM
180
mA
Idle Quiet Standby
Current
/CS>=Vih(min); All banks idle; CKE>=Vih(min);
IDD2Q Addresses and other control inputs stable, Vin=Vref for
140
DQ, DQS and DM
180 mA
Active Power Down
Standby Current
IDD3P
One bank active ; Power down mode; CKE=Low,
tCK=tCK(min)
96
120 mA
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
Active Standby Current
IDD3N
tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS
inputs changing twice per clock cycle; Address and
240
other control inputs changing once per clock cycle
220 mA
Operating Current
IDD4R
Burst=2; Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); IOUT=0mA
1120
1040
Operating Current
IDD4W
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); DQ, DM, and DQS inputs
changing twice per clock cycle
1120
1040 mA
Auto Refresh Current
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz;
distributed refresh
1240
1080
Self Refresh Current
IDD6
CKE=<0.2V; External clock on; tCK
=tCK(min)
Normal
Low Power
40
mA
20
mA
Operating Current -
Four Bank Operation
IDD7
Four bank interleaving with BL=4 Refer to the following
page for detailed test condition
2200
1880 mA
Random Read Current
IDD7A
4banks active read with activate every 20ns, AP(Auto
Precharge) read every 20ns, BL=4, tRCD=3, IOUT=0
mA, 100% DQ, DM and DQS inputs changing twice
per clock cycle; 100% addresses changing once per
clock cycle
2200
1880 mA
Rev. 0.2 / Apr. 2004
9