HYMD564M646AL6-D43 Datasheet, PDF (16/17 Pages) Hynix Semiconductor – Unbuffered DDR SO-DIMM

SERIAL PRESENCE DETECT
Byte#
Function Description
0 Number of Bytes written into serial memory at module
manufacturer
1 Total number of Bytes in SPD device
2 Fundamental memory type
3 Number of row address on this assembly
4 Number of column address on this assembly
5 Number of physical banks on DIMM
6 Module data width
7 Module data width (continued)
8 Module voltage Interface levels(VDDQ)
9 DDR SDRAM cycle time at CAS Latency=2.5(tCK)
10 DDR SDRAM access time from clock at CL=2.5 (tAC)
11 Module configuration type
12 Refresh rate and type
13 Primary DDR SDRAM width
14 Error checking DDR SDRAM data width
15 Minimum clock delay for back-to-back random column
address(tCCD)
16 Burst lengths supported
17 Number of banks on each DDR SDRAM
18 CAS latency supported
19 CS latency
20 WE latency
21 DDR SDRAM module attributes
22 DDR SDRAM device attributes : General
23 DDR SDRAM cycle time at CL=2.0(tCK)
24 DDR SDRAM access time from clock at CL=2.0(tAC)
25 DDR SDRAM cycle time at CL=1.5(tCK)
26 DDR SDRAM access time from clock at CL=1.5(tAC)
27 Minimum row precharge time(tRP)
28 Minimum row activate to row active delay(tRRD)
29 Minimum RAS to CAS delay(tRCD)
30 Minimum active to precharge time(tRAS)
31 Module row density
32 Command and address signal input setup time(tIS)
33 Command and address signal input hold time(tIH)
34 Data signal input setup time(tDS)
35 Data signal input hold time(tDH)
36~40 Reserved for VCSDRAM
41 Minimum active / auto-refresh Time (tRC)
42
Minimum auto-refresh to active / auto-refresh
command period (tRFC)
43 Maximum cycle time (tCK max)
44 Maximum DQS-DQ skew time (tDQSQ)
45 Maximum read data hold skew factor (tQHS)
46~61 Superset Information(may be used in future)
62 SPD Revision code
63 Checksum for Bytes 0~62
HYMD564M646A(L)6-D43/D4/J
Bin Sort : D43(DDR400@CL=3, D4(DDR400@CL=3), J(DDR333@CL=2.5)
Function Supported
D43
D4
J
Hexa Value
D43
D4
J
Note
128 Bytes
80h
256 Bytes
08h
DDR SDRAM
07h
13
0Dh
1
10
0Ah
1
2Bank
02h
64 Bits
40h
-
00h
SSTL 2.5V
04h
5.0ns
5.0ns
6.0ns
50h
50h
60h
2
+/-0.7ns
70h
2
Non-ECC
00h
7.8us & Self refresh
82h
x16
10h
N/A
00h
1 CLK
01h
2,4,8
4 Banks
2, 2.5, 3
2, 2.5
0
1
Differential Clock Input
+/-0.2Voltage tolerance,
Concurrent Auto Precharge
tRAS Lock Out
6.0ns
6.0ns
7.5ns
+/-0.7ns
7.5ns
-
0Eh
04h
1Ch
0Ch
01h
02h
20h
C0h
60h
60h
70h
75h
75h
00h
+/-0.75ns
-
75h
00h
15ns
18ns
18ns
3Ch
48h
48h
10ns
10ns
12ns
28h
28h
30h
15ns
18ns
18ns
3Ch
48h
48h
40ns
40ns
42ns
28h
28h
2Ah
256MB
40h
0.60ns 0.60ns 0.75ns
60h
60h
75h
0.60ns 0.60ns 0.75ns
60h
60h
75h
0.40ns 0.40ns 0.45ns
40h
40h
45h
0.40ns 0.40ns 0.45ns
40h
40h
45h
Undefined
00h
55ns
58ns
60ns
37h
3Ah
3Ch
70ns
70ns
72ns
46h
46h
48h
10ns
10ns
12ns
28h
28h
30h
0.40ns 0.40ns 0.45ns
28h
28h
2Dh
0.50ns 0.50ns 0.55ns
50h
50h
55h
Undefined
00h
Initial release
00h
-
6Fh
8Ah
09h
Rev. 0.2 / Apr. 2004
16