HYMD512G726BF8N-D43 Datasheet, PDF (9/16 Pages) Hynix Semiconductor – Registered DDR SDRAM DIMM

HYMD512G726B(L)F8N-D43/J
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
Symbol
DDR400 (D43)
Min
Max
DDR333 (J)
Min
Max
Row Cycle Time
tRC
55
-
60
-
Auto Refresh Row Cycle Time
tRFC
70
-
72
-
Row Active Time
tRAS
40
70K
42
70K
Active to Read with Auto Precharge Delay
tRAP
tRCD or
tRAS(min)
-
18
-
Row Address to Column Address Delay
tRCD
15
-
18
-
Row Active to Row Active Delay
tRRD
10
-
12
-
Column Address to Column Address Delay
tCCD
1
-
1
-
Row Precharge Time
tRP
15
-
18
-
Write Recovery Time
tWR
15
-
15
-
Write to Read Command Delay
tWTR
2
-
1
-
Auto Precharge Write Recovery + Precharge
Time
(tWR/tCK)
(tWR/tCK)
tDAL
+
-
+
(tRP/tCK)
(tRP/tCK)
CL = 3
5
System Clock Cycle Time
tCK
CL = 2.5
6
10
6
12
12
7.5
12
Clock High Level Width
tCH
0.45
0.55
0.45
0.55
Clock Low Level Width
tCL
0.45
0.55
0.45
0.55
Data-Out edge to Clock edge Skew
tAC
-0.7
0.7
-0.7
0.7
DQS-Out edge to Clock edge Skew
tDQSCK -0.55
0.55
-0.6
0.6
DQS-Out edge to Data-Out edge Skew
tDQSQ
-
0.4
0.45
Data-Out hold time from DQS
tQH
tHP
-tQHS
-
tHP
-tQHS
-
Clock Half Period
tHP
min
(tCL,tCH)
-
min
(tCL,tCH)
-
Data Hold Skew Factor
tQHS
-
0.5
-
0.55
Data-out high-impedance window from CK, /CK tHZ
tAC(Max) -0.7
0.7
Data-out low-impedance window from CK, /CK
tLZ
tAC(min) tAC(Max) -0.7
0.7
Input Setup Time (fast slew rate)
tIS
0.6
-
0.75
-
Input Hold Time (fast slew rate)
tIH
0.6
-
0.75
-
Input Setup Time (slow slew rate)
tIS
0.7
-
0.8
-
Input Hold Time (slow slew rate)
tIH
0.7
-
0.8
-
Input Pulse Width
tIPW
2.2
-
2.2
-
Write DQS High Level Width
tDQSH
0.35
-
0.35
-
Unit
ns
ns
ns
ns
ns
ns
CK
ns
ns
CK
CK
ns
CK
CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
Note
16
15
1, 10
1,9
10
17
17
2,3,5,6
2,3,5,6
2,4,5,6
2,4,5,6
6
Rev. 0.1 / Mar. 2004
9