HYMD264M646BF8-J Datasheet, PDF (9/19 Pages) Hynix Semiconductor – Unbuffered DDR SO-DIMM

HYMD264M646B(L)F8-J/M/K/H/L
DC CHARACTERISTICS II (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Test Condition
Speed
Unit Note
-J -M -K -H -L
Operating Current
One bank; Active - Precharge;
tRC=tRC(min); tCK=tCK(min); DQ,DM and
IDD0 DQS inputs changing twice per clock cycle 1040 1040 960 960 880 mA
; address and control inputs changing once
per clock cycle
Operating Current
One bank; Active - Read - Precharge;
IDD1
Burst Length=2; tRC=tRC(min);
tCK=tCK(min); address and control inputs
1040 1040
960
960
880
mA
changing once per clock cycle
Precharge Power
Down Standby
Current
IDD2P
All banks idle; Power down - mode;
CKE=Low, tCK=tCK(min)
160
mA
Idle Standby Current
/CS=High, All banks idle; tCK=tCK(min);
IDD2F
CKE= High; address and control inputs
changing once per clock cycle. VIN=VREF
480
480
440
440
400
mA
for DQ, DQS and DM
Active Power Down
Standby Current
IDD3P
One bank active; Power down mode;
CKE=Low, tCK=tCK(min)
240
mA
Active Standby
Current
/CS=HIGH; CKE=HIGH; One bank; Active-
Precharge; tRC=tRAS(max);
IDD3N
tCK=tCK(min); DQ, DM and DQS inputs
changing twice per clock cycle; Address
560 560 520 520 480 mA
and other control inputs changing once per
clock cycle
Operating Current
IDD4R
Burst=2; Reads; Continuous burst; One
bank active; Address and control inputs
changing once per clock cycle;
tCK=tCK(min); IOUT=0mA
1440 1440 1280 1280 1200
Operating Current
IDD4W
Burst=2; Writes; Continuous burst; One
bank active; Address and control inputs
changing once per clock cycle;
tCK=tCK(min); DQ, DM and DQS inputs
changing twice per clock cycle
1520 1520 1440 1440 1360 ^mA
Auto Refresh Current
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at
100Mhz, 10*tCK for DDR266A &
DDR266B at 133Mhz; distributed refresh
1520 1520 1440 1440 1360
Self Refresh Current
IDD6
CKE=<0.2V; External clock
on; tCK =tCK(min)
Normal
Low Power
48
24
mA
mA
Operating Current -
Four Bank Operation
IDD7
Four bank interleaving with BL=4 Refer to
the following page for detailed test
2240 2240 2160 2160 2080 mA
condition
Rev. 0.2 / Apr. 2004
9