HYMD264M646BF8-J Datasheet, PDF (2/19 Pages) Hynix Semiconductor – Unbuffered DDR SO-DIMM

64Mx64 bits
Unbuffered DDR SO-DIMM
HYMD264M646B(L)F8-J/M/K/H/L
DESCRIPTION
Hynix HYMD264M646B(L)F8-J/M/K/H/L series is unbuffered 200-pin double data rate Synchronous DRAM Small Out-
line Dual In-Line Memory Modules (SO-DIMMs) which are organized as 64Mx64 high-speed memory arrays. Hynix
HYMD264M646B(L)F8-J/M/K/H/L series consists of sixteen 32Mx8 DDR SDRAM in FBGA packages on a 200pin
glass-epoxy substrate. Hynix HYMD264M646B(L)F8-J/M/K/H/L series provide a high performance 8-byte interface in
67.60mmX 31.75mm form factor of industry standard. It is suitable for easy interchange and addition.
Hynix HYMD232M646B(L)F8-J/M/K/H/L series is designed for high speed of up to 166MHz and offers fully synchro-
nous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control
inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on
both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high
bandwidth. All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable
latencies and burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD264M646B(L)F8-J/M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect func-
tion is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to
identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
• 200-pin small outline dual in-line memory module
(SO-DIMM)
• Bidirectional data strobes synchronized with output
data for read and input data for write
• 2.6V +/- 0.1V VDD and VDDQ Power supply
• Programmable CAS Latency 3 (clock) for DDR400,
• Double data rate architecture; two data accesses per
2.5(clock) for DDR333
clock cycle
• Programmable Burst Length 2/4/8 with both sequen-
• Differential Clock inputs (CK & /CK)
tial and interleave mode
• Data inputs on DQS centers when write
• Internal four bank operations with single pulsed RAS
(centered DQ)
• Auto & Self refresh mode
; 8192 refresh cycles / 64ms
ORDERING INFORMATION
Part No.
Power Supply Clock Frequency
HYMD264M646B(L)F8-J
HYMD264M646B(L)F8-M
HYMD264M646B(L)F8-K
HYMD264M646B(L)F8-H
HYMD264M646B(L)F8-L
VDD=2.5V
VDDQ=2.5V
166MHz (*DDR333)
133MHz (*DDR266)
133MHz (*DDR266A)
133MHz (*DDR266B)
100MHz (*DDR200)
CL-tRCD-tRP
Form Factor
2.5-3-3
2-2-2
2-3-3
2.5-3-3
2.5-3-3
200pin Unbuffered SO-DIMM
67.6mm x 31.75mm x 1mm
* JEDEC Defined Specifications compliant
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.2 / Apr. 2004
2