HYMD264G726BL4M-M Datasheet, PDF (9/17 Pages) Hynix Semiconductor – Low Profile Registered DDR SDRAM DIMM

HYMD264G726B(L)4M-M/K/H/L
DC CHARACTERISTICS II (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Test Condition
Speed
Unit Note
-M -K -H -L
Operating Current
IDD0
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs
changing twice per clock cycle; address and
control inputs changing once per clock cycle
2810 2630 2630 2450 mA
Operating Current
IDD1
One bank; Active - Read - Precharge; Burst
Length=2; tRC=tRC(min); tCK=tCK(min);
address and control inputs changing once per
clock cycle
2810 2630 2630 2450 mA
Precharge Power
Down Standby Current
IDD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
830
mA
Idle Standby Current
/CS=High, All banks idle; tCK=tCK(min); CKE=
IDD2F
High; address and control inputs changing once
per clock cycle. VIN = VREF for DQ, DQS and
1550
1460
1460
1370
mA
DM
Active Power Down
Standby Current
One bank active; Power down mode;
IDD3P _{CKE=Low, tCK=tCK(min)}
920
mA
Active Standby Current
IDD3N
/CS=HIGH; CKE=HIGH; One bank; Active-
Precharge; tRC=tRAS(max); tCK=tCK(max);
DQ, DM and DQS inputs changing twice per
clock cycle; Address and other control inputs
changing once per clock cycle
1730 1640 1640 1550 mA
Operating Current
IDD4R
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing
once per clock cycle; tCK=tCK(min);
IOUT=0mA
3710 3350 3350 3170
Operating Current
Burst=2; Writes; Continuous burst; One bank
active; Address and control inputs changing
mA
IDD4W _{once per clock cycle; tCK=tCK(min); DQ, DM,} 3890 3710 3710 3530
and DQS inputs changing twice per clock cycle
Auto Refresh Current
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz; 3590
distributed refresh
3410
3410
3230
Normal
404
mA
Self Refresh Current
IDD6
CKE=<0.2V; External clock on;
tCK=tCK(min)
Low Power
377
mA
Operating Current -
Four Bank Operation
IDD7
Four bank interleaving with BL=4 Refer to the
following page for detailed test condition
5510 5330 5330 5150 mA
Rev. 0.2/ Dec. 2003
9