HYMD232G726BF8-J Datasheet, PDF (9/16 Pages) Hynix Semiconductor – Registered DDR SDRAM DIMM

HYMD232G726B(L)F8-J
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
Row Cycle Time
Auto Refresh Row Cycle Time
Row Active Time
Active to Read with Auto Precharge Delay
Row Address to Column Address Delay
Row Active to Row Active Delay
Column Address to Column Address Delay
Row Precharge Time
Write Recovery Time
Write to Read Command Delay
Auto Precharge Write Recovery + Precharge Time
System Clock Cycle Time
Clock High Level Width
Clock Low Level Width
Data-Out edge to Clock edge Skew
DQS-Out edge to Clock edge Skew
DQS-Out edge to Data-Out edge Skew
Data-Out hold time from DQS
CL = 2.5
CL = 2
Clock Half Period
Data Hold Skew Factor
Valid Data Output Window
Data-out high-impedance window from CK, /CK
Data-out low-impedance window from CK, /CK
Input Setup Time (fast slew rate)
Input Hold Time (fast slew rate)
Input Setup Time (slow slew rate)
Input Hold Time (slow slew rate)
Symbol
tRC
tRFC
tRAS
tRAP
tRCD
tRRD
tCCD
tRP
tWR
tWTR
tDAL
tCK
tCH
tCL
tAC
tDQSCK
tDQSQ
tQH
tHP
tQHS
tDV
tHZ
tLZ
tIS
tIH
tIS
tIH
DDR333
Min
Max
60
-
72
-
42
70K
18
-
18
-
12
-
1
-
18
-
15
-
1
-
(tWR/tCK)
+
-
(tRP/tCK)
6
12
7.5
12
0.45
0.55
0.45
0.55
-0.7
0.7
-0.6
0.6
-
0.45
tHP
-tQHS
-
min
(tCL,tCH)
-
-
0.55
tQH-tDQSQ
-0.7
0.7
-0.7
0.7
0.75
-
0.75
-
0.8
-
0.8
-
Unit
Note
ns
ns
ns
ns
16
ns
ns
CK
ns
ns
CK
CK
15
ns
ns
CK
CK
ns
ns
ns
ns
1, 10
ns
1,9
ns
10
ns
ns
17
ns
17
ns
2,3,5,6
ns
2,3,5,6
ns
2,4,5,6
ns
2,4,5,6
Rev. 0.1 / Mar. 2004
9