HYMD216M646CL6-J Datasheet, PDF (9/20 Pages) Hynix Semiconductor – Unbuffered DDR SO-DIMM

HYMD216M646C(L)6-J/M/K/H/L
DC CHARACTERISTICS II (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Test Condition
Speed
Unit Note
-J -M -K -H -L
Operating Current
IDD0
One bank; Active - Precharge;
tRC=tRC(min); tCK=tCK(min); DQ,DM and
DQS inputs changing twice per clock cycle;
address and control inputs changing once
per clock cycle
420 420 380 380 360 mA
Operating Current
IDD1
One bank; Active - Read - Precharge; Burst
Length=2; tRC=tRC(min); tCK=tCK(min);
address and control inputs changing once
600 600 520 520 480 mA
per clock cycle
Precharge Power Down
All banks idle; Power down mode; CKE=Low,
Standby Current
IDD2P _tCK=tCK(min)
80
mA
Idle Standby Current
IDD2F
/CS=High, All banks idle; tCK=tCK(min);
CKE= High; address and control inputs
changing once per clock cycle. VIN=VREF
for DQ, DQS and DM
200 200 160 160 140 mA
Active Power Down
Standby Current
One bank active ; Power down mode;
IDD3P _{CKE=Low, tCK=tCK(min)}
100
mA
/CS>=Vih(min); All banks idle;
Idle Quiet Standby
Current
IDD2Q
CKE>=Vih(min); Addresses and other
control inputs stable, Vin=Vref for DQ, DQS
TBD
mA
and DM
Active Standby Current
/CS=HIGH; CKE=HIGH; One bank; Active-
Precharge; tRC=tRAS(max); tCK=tCK(min);
IDD3N DQ, DM and DQS inputs changing twice per 240 240 200 200 200 mA
clock cycle; Address and other control inputs
changing once per clock cycle
Operating Current
IDD4R
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing
once per clock cycle; tCK=tCK(min);
1160 1160 1000 1000 760
IOUT=0mA
Operating Current
Burst=2; Writes; Continuous burst; One bank
IDD4W
active; Address and control inputs changing
once per clock cycle; tCK=tCK(min); DQ, DM 1160 1160 1000 1000 760
mA
and DQS inputs changing twice per clock
cycle
Auto Refresh Current
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at
100Mhz, 10*tCK for DDR266A & DDR266B 920 920 840 840 780
at 133Mhz; distributed refresh
Self Refresh Current
IDD6
CKE=<0.2V; External clock on; ^Normal
tCK =tCK(min)
Low Power
12
6
mA
mA
Operating Current -
Four Bank Operation
IDD7
Four bank interleaving with BL=4 Refer to
the following page for detailed test condition
1340 1340 1300 1300 1160
mA
4banks active read with activate every 20ns,
AP(Auto Precharge) read every 20ns, BL=4,
Random Read Current
IDD7A
tRCD=3, IOUT=0 mA, 100% DQ, DM and
DQS inputs changing twice per clock cycle;
TBD
mA
100% addresses changing once per clock
cycle
Rev. 0.3 / Oct. 2004
9