HY62256A Datasheet, PDF (9/14 Pages) Hynix Semiconductor – 32Kx8bit CMOS SRAM

-sram/62256alt1
http://www.hea.com/hean2/sram/62256alt1.htm
HYUNDAI ELECTRONICS AMERICA
HY62256A-I
32K x 8bit CMOS SRAM
TIMING DIAGRAM
READ CYCLE 1
TIMING INFORMATION
Note (READ CYCLE):
1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open
circuit conditions and are not referenced to output voltage levels.
2. At any given temperature and voltage condition, tCHZ max. is less than tCLZ min.
both for a given device and from device to device.
3. /WE is high for the read cycle.
READ CYCLE 2
Note (READ CYCLE):
1. /WE is high for the read cycle.
2. Device is continuously selected /CS= VIL.
3. /OE =VIL.
WRITE CYCLE 1 (/OE Clocked)
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