HY62256A Datasheet, PDF (11/14 Pages) Hynix Semiconductor – 32Kx8bit CMOS SRAM

-sram/62256alt1
http://www.hea.com/hean2/sram/62256alt1.htm
DATA RETENTION CHARACTERISTIC
TA= 0°C to 70°C (normal) /-40°C to 85°C (E.T.)
Symbol
Parameter
Test Condition Min Typ Max Unit
VDR Vcc for Data Re! ention
/CS >= Vcc-0.2V
Vss <= VIN <= 2
Vcc
-- V
ICCDR
Data
Retention
Current
HY62256A
HY62256A-1
Vcc = 3.0V _{L -}
/CS >= Vcc
-0.2V
LL -
Vss <= VIN
<= Vcc
L-
1 50 uA
1 15(2) uA
1 50 uA
tCDR
Chip Disable to Data Retention
Time
See Data
Retention Timing
0
- - ns
tR
Operating Recovery Time
Diagram
tRC(3) - - ns
Notes
1. Typical values are under the condition of TA = 25°C
2. 3uA max. at TA= 0°C to 40°C
3. tRC is read cycle time.
Data Retention Timing Diagram
RELIABILITY SPEC.
TEST MODE
TEST SPEC.
ESD
HBM
MM
>= 2000V
>= 250V
LATCH-UP
<= -100mA
>= 100mA
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