HYMP112L72CP8D5-C4 Datasheet, PDF (8/26 Pages) Hynix Semiconductor – 240pin Fully Buffered DDR2 SDRAM DIMMs

1240pin Fully Buffered DDR2 SDRAM DIMMs
Architecture
Advanced Memory Buffer Pin Description
Pin Namel
SCK
SCK
PN[13:0]
PN[13:0]
PS[9:0]
PS[9:0]
SN[13:0]
SN[13:0]
SS[9:0]
SS[9:0]
FBDRES
DQS[8:0]
DQS[8:0]
DQS[17:9]/DM[8:0]
DQS[17:9]
DQ[63:0]
CB[7:0]
A[15:0]A,A[15:0]B
BA[2:0]A,BA[2:0]B
RASA,RASB
CASA,CASB
WEA,WEB
ODTA,ODTB
CKE[1:0]A,CKE[1:0]B
CS[1:0]A,CS[1:0]B
CLK[3:0]
CLK[3:0]
DDRC_C14
DDRC_B18
DDRC_C18
DDRC_B12
DDRC_C12
Pin Description
FB-DIMM Channel Signals
System Clock Input, positive line
System Clock Input, negative line
Primary Northbound Data, positive lines
Primary Northbound Data, negative lines
Primary Southbound Data, positive lines
Primary Southbound Data, negative lines
Secondary Northbound Data, positive lines
Secondary Northbound Data, negative lines
Secondary Southbound Data, positive lines
Secondary Southbound Data, negative lines
To an external precision calibration resistor connected to Vcc
DDR2 Interface Signals
Data Strobes, positive lines
Data Strobes, negative lines
Data Strobes(x4 DRAM only), positive lines. These signals are driven low to x8
DRAM on writes.
Data Strobes(x4 DRAM only), negative lines
Data
Checkbits
Addresses. A10 is part of the pre-charge command
Bank Addresses
Part of command, with CAS, WE and CS[1:0]
Part of command, with RAS, WE and CS[1:0]
Part of command , with RAS, WE and CS[1:0]
On-die Termination Enable
Clock Enable(one per rank)
Chip Select(One per rank)
CLK[1:0] used on 9 and 18 device DIMMs, CLK[3:0] used on 36 device DIMMs.
CLK[3:2] should be output disabled when not in use.
Negative lines for CLK[3:0]
DDR Compensation: Common return pin for DDRC_B18 and DDRC_C18
DDR Compensation: Resistor connected to common return pin DDRC_C14
DDR Compensation: Resistor connected to common return pin DDRC_C14
DDR Compensation: Resistor connected to VSS
DDR Compensation: Resistor connected to VDD
Count
99
1
1
14
14
10
10
14
14
10
10
1
175
9
9
9
9
64
8
32
6
2
2
2
2
4
4
4
4
1
1
1
1
1
Rev 1.0 / June 2008
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