HYMP112L72CP8D5-C4 Datasheet, PDF (20/26 Pages) Hynix Semiconductor – 240pin Fully Buffered DDR2 SDRAM DIMMs

1240pin Fully Buffered DDR2 SDRAM DIMMs
IDD Specification and Conditions
I_DD Measurement Conditions
Symbol
Idle_0
Idle_1
Idle_2
Active_1
Active_2
L0s
Training
(for AMB spec, not in
SPD)
Conditions
Idle Current, single or last DIMML0 state, idle (0 BW)Primary channel enabled, Sec-
ondary Channel Disabled CKE high. Command and address lines stable. DRAM clock
active.
Idle Current, first DIMML0 state, idle (0 BW)Primary and Secondary channels
enabled CKE high. Command and address lines stable. DRAM clock active.
Idle Current, DRAM power downL0 state, idle (0 BW)Primary and Secondary chan-
nels enabledCKE low. Command and address lines floated. DRAM clock active, ODT
and CKE driven low.
Active PowerL0 state. 50% DRAM BW, 67% read, 33% write.
Primary and Secondary channels enabled. DRAM clock active, CKE high.
Active Power, data pass throughL0 state. 50% DRAM BW to downstream DIMM,
67% read, 33% write. Primary and Secondary channels enabled CKE high.
Command and address lines stable. DRAM clock active.
Channel Standby Average power over 42 frames where the channel enters and exits
L0sDRAMs Idle (0 BW). CKE low. Command and address lines floated.
Dram clocks active, ODE and CKE driven low.
Training Primary and Secondary channels enabled.100% toggle on all channels
lanes.DRAMs idle (0 BW).CKE high. Command and address lines stable.DRAM clock
active.
Rev 1.0 / June 2008
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