HYMD232G726DF8N-D43 Datasheet, PDF (8/23 Pages) Hynix Semiconductor – 184pin Registered DDR SDRAM DIMMs

184pin Registered DDR SDRAM DIMMs
IDD SPECIFICATION AND CONDITIONS (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
256MB, 32M x 72 ECC Registered DIMM: HYMD232G726DF[P]8N
Symbol
Test Condition
Speed
Unit
DDR400B
DDR333
IDD0
IDD1
IDD2P
IDD2F
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing
twice per clock cycle; address and control inputs
changing once per clock cycle
One bank; Active - Read - Precharge; Burst
Length=2; tRC=tRC(min); tCK=tCK(min); address
and control inputs changing once per clock cycle
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=High, All banks idle; tCK=tCK(min); CKE= High;
address and control inputs changing once per clock
cycle. VIN=VREF for DQ, DQS and DM
One bank active; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS
inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle
Burst=2; Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); IOUT=0mA
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); DQ, DM and DQS inputs chang-
ing twice per clock cycle
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz; distrib-
uted refresh
CKE=<0.2V; External clock on; tCK _Normal
=tCK(min)
Low Power
1460
1550
740
1190
785
1100
2270
2270
1700
377
364
1370
mA
1550
mA
740
mA
1100
mA
785
mA
1055
mA
2090
mA
2090
mA
1700
mA
377
mA
364
mA
IDD7
Four bank interleaving with BL=4 Refer to the follow-
ing page for detailed test condition
2720
2630
mA
Note
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.1 /May. 2005
8