HYMD232G726DF8N-D43 Datasheet, PDF (10/23 Pages) Hynix Semiconductor – 184pin Registered DDR SDRAM DIMMs

184pin Registered DDR SDRAM DIMMs
IDD SPECIFICATION AND CONDITIONS (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
1GB, 64M x 72 ECC Registered DIMM: HYMD264G726DF[P]4
Symbol
Test Condition
Speed
Unit
DDR400B
DDR333
IDD0
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing
twice per clock cycle; address and control inputs
changing once per clock cycle
3170
2900
mA
IDD1
One bank; Active - Read - Precharge; Burst
Length=2; tRC=tRC(min); tCK=tCK(min); address
and control inputs changing once per clock cycle
3350
3260
mA
IDD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
1010
1010
mA
IDD2F
/CS=High, All banks idle; tCK=tCK(min); CKE= High;
address and control inputs changing once per clock
cycle. VIN=VREF for DQ, DQS and DM
2630
2360
mA
IDD3P
One bank active; Power down mode; CKE=Low,
tCK=tCK(min)
1190
1190
mA
IDD3N
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS
inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle
2450
2270
mA
IDD4R
Burst=2; Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); IOUT=0mA
4430
4160
mA
IDD4W
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); DQ, DM and DQS inputs chang-
ing twice per clock cycle
4430
4160
mA
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz; distrib-
uted refresh
3950
3860
mA
CKE=<0.2V; External clock on; tCK Normal
458
IDD6 =tCK(min)
Low Power
404
458
mA
404
mA
IDD7
Four bank interleaving with BL=4 Refer to the follow-
ing page for detailed test condition
6050
5780
mA
Note
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.1 /May. 2005
10