HYMD216M726AL6-J Datasheet, PDF (8/19 Pages) Hynix Semiconductor – Unbuffered DDR SO-DIMM

HYMD216M726A(L)6-J/M/K/H/L
DC CHARACTERISTICS II (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Test Condition
Speed
Unit Note
-J -M -K -H -L
Operating Current
One bank; Active - Precharge; tRC=tRC(min);
IDD0
tCK=tCK(min); DQ,DM and DQS inputs
changing twice per clock cycle; address and
525 525 475 475 450 mA
control inputs changing once per clock cycle
Operating Current
One bank; Active - Read - Precharge; Burst
IDD1
Length=2; tRC=tRC(min); tCK=tCK(min);
address and control inputs changing once per
750
750
650
650
600
mA
clock cycle
Precharge Power
Down Standby Current
IDD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
100
mA
Idle Standby Current
/CS=High, All banks idle; tCK=tCK(min);
IDD2F
CKE= High; address and control inputs
changing once per clock cycle. VIN=VREF for
250
250
200
200
175
mA
DQ, DQS and DM
Active Power Down
Standby Current
IDD3P
One bank active; Power down mode;
CKE=Low, tCK=tCK(min)
125
mA
Idle Quiet Standby
Current
IDD2Q
/CS>=Vih(min); All banks idle;
CKE>=Vih(min); Addresses and other control
inputs stable, Vin=Vref for DQ, DQS and DM
TBD
mA
Active Standby
Current
/CS=HIGH; CKE=HIGH; One bank; Active-
Precharge; tRC=tRAS(max); tCK=tCK(min);
IDD3N DQ, DM and DQS inputs changing twice per 300 300 250 250 250 mA
clock cycle; Address and other control inputs
changing once per clock cycle
Operating Current
Burst=2; Reads; Continuous burst; One bank
IDD4R
active; Address and control inputs changing
once per clock cycle; tCK=tCK(min);
1450 1450 1250 1250 950
IOUT=0mA
Operating Current
Burst=2; Writes; Continuous burst; One bank
active; Address and control inputs changing
IDD4W once per clock cycle; tCK=tCK(min); DQ, DM 1450 1450 1250 1250 950
mA
and DQS inputs changing twice per clock
cycle
Auto Refresh Current
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at
100Mhz, 10*tCK for DDR266A & DDR266B at 1150 1150 1050 1050 975
133Mhz; distributed refresh
Self Refresh Current
IDD6
CKE=<0.2V; External clock on; ^Normal
tCK =tCK(min)
Low Power
15
7.5
mA
mA
Operating Current -
Four Bank Operation
IDD7
Four bank interleaving with BL=4 Refer to the
following page for detailed test condition
1675
1675
1625
1625
1450
mA
Random Read Current
IDD7A
4banks active read with activate every 20ns,
AP(Auto Precharge) read every 20ns, BL=4,
tRCD=3, IOUT=0 mA, 100% DQ, DM and
DQS inputs changing twice per clock cycle;
100% addresses changing once per clock
cycle
TBD
mA
Rev. 0.3/Oct. 02
8