HY62SF16406E Datasheet, PDF (8/11 Pages) Hynix Semiconductor – 256Kx16bit full CMOS SRAM

HY62SF16406E Series
Notes:
1. A write occurs during the overlap of a low /WE, a low /CS1, a high CS2 and a low /UB and/or /LB .
2. tWR is measured from the earlier of /CS1, /LB, /UB, or /WE going high or CS2 going low to the
end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
output must not be applied.
4. If the /CS1, /LB and /UB low transition and CS2 high transition occur simultaneously with the /WE low
transition or after the /WE transition, outputs remain in a high impedance state.
5. Q(data out) is the same phase with the write data of this write cycle.
6. Q(data out) is the read data of the next address.
7. Transition is measured + 200mV from steady state.
This parameter is sampled and not 100% tested.
8. /CS1 in high for the standby, low for active
CS2 in low for the standby, high for active.
/UB and /LB in high for the standby, low for active
DATA RETENTION ELECTRIC CHARACTERISTIC
TA = -40°C to 85°C
Symbol
Parameter
VDR
Vcc for Data Retention
Iccdr
Data Retention Current
tCDR
tR
Chip Deselect to Data
Retention Time
Operating Recovery Time
Test Condition
/CS1 > Vcc - 0.2V or
CS2 < Vss + 0.2V or
/UB, /LB > Vcc - 0.2V,
VIN > Vcc - 0.2V or
VIN < Vss + 0.2V
Vcc=1.5V,
/CS1 > Vcc - 0.2V or
SL
CS2 < Vss + 0.2V or
/UB, /LB > Vcc - 0.2V
VIN > Vcc - 0.2V or
LL
VIN < Vss + 0.2V
See Data Retention Timing Diagram
Notes:
1. Typical values are under the condition of TA = 25°C.
2. Typical value are sampled and not 100% tested
Min Typ^1. Max Unit
1.2
-
2.3
V
-
0.1
3
uA
-
0.1
6
uA
0
-
tRC
-
-
ns
-
ns
Rev.02 / May.02
7