HY62LF16206A Datasheet, PDF (8/11 Pages) Hynix Semiconductor – 128Kx16bit full CMOS SRAM

HY62LF16206A-LT12C
DATA RETENTION ELECTRIC CHARACTERISTIC
TA = 0°C to 70°C
Symbol
Parameter
Test Condition
Min. Typ. Max. Unit
VDR
Vcc for Data Retention
/CS1 > Vcc - 0.2V or CS2 < Vss+0.2V 1.2
- 2.7 V
or /UB = /LB > Vcc-0.2V,
VIN > Vcc - 0.2V or VIN < Vss + 0.2V
ICCDR Data Retention Current Vcc=1.5V, /CS1 > Vcc - 0.2V,
-
- 100 uA
CS2 < Vss+0.2V,
/UB = /LB > Vcc-0.2V or
VIN > Vcc - 0.2V or VIN < Vss + 0.2V
tCDR Chip Deselect to Data
See Data Retention Timing Diagram
0
-
-
ns
Retention Time
tR
Operating Recovery Time
tRC(3) -
-
ns
Notes:
1. Typical values are under the condition of TA = 25°C.
2. Typical Values are sampled and not 100% tested
3. tRC is read cycle time.
DATA RETENTION TIMING DIAGRAM 1
VCC
2.3V
VIH
VDR
/CS1
VSS
DATA RETENTION MODE
tCDR
tR
CS1>VCC-0.2V
DATA RETENTION TIMING DIAGRAM 2
VCC
2.3V
CS2
VDR
0.4V
VSS
DATA RETENTION MODE
tCDR
tR
CS2<0.2V
Rev.05 /Apr. 2002
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