HY62LF16206A Datasheet, PDF (7/11 Pages) Hynix Semiconductor – 128Kx16bit full CMOS SRAM

WRITE CYCLE 1 (1,4,8) (/WE Controlled)
tWC
ADDR
/CS1
tCW
HY62LF16206A-LT12C
tWR(2)
CS2
/UB,/LB
/W E
Data In
Data
Out
tAS
High-Z
tAW
tBW
tWP
tWHZ(3,7)
tDW
Data Valid
tDH
tOW
(5) (6)
WRITE CYCLE 2 (1,4,8) (/CS1, CS2 Controlled)
ADDR
tAS
tWC
tCW
/CS1
tAW
CS2
tBW
/UB,/LB
/W E
tWP
Data In
High-Z
t W R (2)
tDW
tDH
Data Valid
Data
Out
High-Z
Notes:
1. A write occurs during the overlap of a low /WE, a low /CS1, a high CS2 and low /UB and/or /LB.
2. tWR is measured from the earlier of /CS, /LB, /UB, or /WE going high or CS2 going low to the end of
write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
output must not be applied.
4. If the /CS1, /LB and /UB low transition with CS2 high transition occur simultaneously with the /WE low
transition or after the /WE transition, outputs remain in a high impedance state.
5. Q(data out) is the same phase with the write data of this write cycle.
6. Q(data out) is the read data of the next address.
7. Transition is measured ¡ ¾200mV from steady state.
This parameter is sampled and not 100% tested.
8. /CS1 in high for the standby, low for active. CS2 in low for the standby, high for active.
/UB and /LB in high for the standby, low for active
Rev.05 /Apr. 2002
6