GM76V256C Datasheet, PDF (8/11 Pages) Hynix Semiconductor – 32K x8 bit 3.3V Low Power CMOS slow SRAM

GM76V256C Series
Notes(WRITE CYCLE):
1. A write occurs during the overlap of a low /CS and a low /WE. A write begins at the latest transition
among /CS going low and /WE going low: A write ends at the earliest transition among /CS going high
and /WE going high. tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the later of /CS going low to the end of write .
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends as /CS,
or /WE going high.
5. If /OE and /WE are in the read mode during this period, and the I/O pins are in the output low-Z state,
input of opposite phase of the output must not be applied because bus contention can occur.
6. If /CS goes low simultaneously with /WE going low, or after /WE going low, the outputs remain in high
impedance state.
7. DOUT is the same phase of the latest written data in this write cycle.
8. DOUT is the read data of the new address.
DATA RETENTION CHARACTERISTIC
TA=0°C to 70°C (Normal)
Symbol
Parameter
Test Condition
VDR
Vcc for Data Retention CS > Vcc-0.2V,
VIN > Vcc - 0.2V or VIN < Vss + 0.2V
ICCDR Data Retention Current Vcc = 3.0V,
L
/CS > Vcc - 0.2V,
LL
VIN > Vcc - 0.2V or
LE
VIN < Vss + 0.2V
LLE
tCDR Chip Deselect to Data
See Data Retention
Retention Time
tR
Operating Recovery Time Timing Diagram
Notes
1. Typical values are under the condition of TA = 25°C.
2. tRC is read cycle time.
Min Typ Max Unit
2.0
-
-
V
-
1 15 uA
-
0.5 7 uA
-
1 20 uA
-
0.5 10 uA
0
-
-
ns
tRC(2) -
-
ns
DATA RETENTION TIMING DIAGRAM
VCC
3.0V
2.2V
VDR
CS
VSS
DATA RETENTION MODE
tCDR
tR
CS>VCC-0.2V
Rev 02 / Apr. 2001
7