HYMD564G726BF8N-D43 Datasheet, PDF (7/20 Pages) Hynix Semiconductor – 184pin Registered DDR SDRAM DIMMs

184pin Registered DDR SDRAM DIMMs
IDD SPECIFICATION AND CONDITIONS (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
512MB, 64Mb x 72 ECC Registered DIMM: HYMD564G726BF[P]8N
Symbol
Test Condition
IDD0
IDD1
IDD2P
IDD2F
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing twice
per clock cycle; address and control inputs changing
once per clock cycle
One bank; Active - Read - Precharge; Burst Length=2;
tRC=tRC(min); tCK=tCK(min); address and control
inputs changing once per clock cycle
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=High, All banks idle; tCK=tCK(min); CKE= High;
address and control inputs changing once per clock
cycle. VIN=VREF for DQ, DQS and DM
One bank active; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS
inputs changing twice per clock cycle; Address and other
control inputs changing once per clock cycle
Burst=2; Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); IOUT=0mA
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); DQ, DM and DQS inputs changing
twice per clock cycle
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK
for DDR266A & DDR266B at 133Mhz; distributed refresh
CKE=<0.2V; External clock on; tCK
=tCK(min)
Normal
Low Power
Four bank interleaving with BL=4 Refer to the following
page for detailed test condition
Speed
DDR400B
DDR333
2000
1910
2450
540
965
558
1100
2270
540
965
558
1055
3170
2900
3170
3350
495
473
5510
2900
3170
495
473
4790
Unit Note
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev.1.1 /May. 2005
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