HYMD232M726A8-J Datasheet, PDF (7/17 Pages) Hynix Semiconductor – Unbuffered DDR SO-DIMM

HYMD232M726A(L)8-J/M/K/H/L
DC CHARACTERISTICS II (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Test Condition
Speed
Unit Note
-J -M -K -H -L
Operating Current
One bank; Active - Precharge;
tRC=tRC(min); tCK=tCK(min); DQ,DM and
IDD0 DQS inputs changing twice per clock cycle ; 945 945 855 855 810 mA 1
address and control inputs changing once per
clock cycle
Operating Current
One bank; Active - Read - Precharge; Burst
Length=2; tRC=tRC(min); tCK=tCK(min);
IDD1 _{address and control inputs changing once per} 1350 1350 1170 1170 1080 mA 1
clock cycle
Precharge Power
Down Standby
Current
IDD2P
All banks idle; Power down - mode;
CKE=Low, tCK=tCK(min)
180
mA 1
/CS=High, All banks idle; tCK=tCK(min);
Idle Standby Current
IDD2F
CKE= High; address and control inputs
changing once per clock cycle. VIN=VREF
450 450 360 360 315 mA
1
for DQ, DQS and DM
Active Power Down
Standby Current
IDD3P
One bank active; Power down mode;
CKE=Low, tCK=tCK(min)
225
mA 1
Idle Quiet Standby
Current
IDD2Q
/CS>=Vih(min); All banks idle;
CKE>=Vih(min); Addresses and other control
inputs stable, Vin=Vref for DQ, DQS and DM
TBD
mA
Active Standby
Current
/CS=HIGH; CKE=HIGH; One bank; Active-
Precharge; tRC=tRAS(max); tCK=tCK(min);
IDD3N DQ, DM and DQS inputs changing twice per 540 540 450 450 450 mA 1
clock cycle; Address and other control inputs
changing once per clock cycle
Burst=2; Reads; Continuous burst; One bank
Operating Current
active; Address and control inputs changing
IDD4R _{once per clock cycle; tCK=tCK(min);}
2610 2610 2250 2250 1710
1
IOUT=0mA
Operating Current
Burst=2; Writes; Continuous burst; One bank
IDD4W
active; Address and control inputs changing
once per clock cycle; tCK=tCK(min); DQ, DM
2610
2610
2250
2250
1710
mA
1
and DQS inputs changing twice per clock
cycle
tRC=tRFC(min) - 8*tCK for DDR200 at
Auto Refresh Current IDD5 100Mhz, 10*tCK for DDR266A & DDR266B 2070 2070 1890 1890 1755
1
at 133Mhz; distributed refresh
Self Refresh Current
IDD6
CKE=<0.2V; External clock on; ^Normal
tCK =tCK(min)
Low Power
27
13.5
mA 1
mA 1
Operating Current -
Four Bank Operation
IDD7
Four bank interleaving with BL=4 Refer to the
following page for detailed test condition
2835
2835
2745
2745
2520
mA
1
4banks active read with activate every 20ns,
AP(Auto Precharge) read every 20ns, BL=4,
Random Read
Current
IDD7A
tRCD=3, IOUT=0 mA, 100% DQ, DM and
DQS inputs changing twice per clock cycle;
TBD
mA
100% addresses changing once per clock
cycle
Rev. 0.2/Oct. 02
7