HYMD232M726A8-J Datasheet, PDF (1/17 Pages) Hynix Semiconductor – Unbuffered DDR SO-DIMM

DESCRIPTION
32Mx72 bits
Unbuffered DDR SO-DIMM
HYMD232M726A(L)8-J/M/K/H/L
Hynix HYMD232M726A(L)8-J/M/K/H/L series is unbuffered 200-pin double data rate Synchronous DRAM Small Out-
line Dual In-Line Memory Modules (SO-DIMMs) which are organized as 32Mx72 high-speed memory arrays. Hynix
HYMD232M726A(L)8-J/M/K/H/L series consists of nine 32Mx8 DDR SDRAM in 400mil TSOP II packages on a 200pin
glass-epoxy substrate.
Hynix HYMD232M726A(L)8-J/M/K/H/L series is designed for high speed of up to 166MHz and offers fully synchro-
nous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control
inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on
both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high
bandwidth. All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable
latencies and burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD232M726A(L)8-J/M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect func-
tion is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to
identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
• 256MB (32M x 72) Unbuffered DDR SO-DIMM
based on 32Mx8 DDR SDRAM
• Data inputs on DQS centers when write (centered
DQ)
• JEDEC Standard 200-pin small outline dual in-line
memory module (SO-DIMM)
• Data strobes synchronized with output data for read
and input data for write
• 2.5V +/- 0.2V VDD and VDDQ Power supply
• Programmable CAS Latency 2 / 2.5 supported
• All inputs and outputs are compatible with SSTL_2
interface
• Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
• Fully differential clock operations (CK & /CK) with
• tRAS Lock-out function supported
100MHz/125MHz/133MHz/166MHz
• Internal four bank operations with single pulsed RAS
•
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
•
Auto refresh and self refresh supported
of the clock
• 8192 refresh cycles / 64ms
• Data(DQ), Data strobes and Write masks latched on
both rising and falling edges of the clock
ORDERING INFORMATION
Part No.
HYMD232M726A(L)8-J
HYMD232M726A(L)8-M
HYMD232M726A(L)8-K
HYMD232M726A(L)8-H
HYMD232M726A(L)8-L
Power Supply
VDD=2.5V
VDDQ=2.5V
Clock Frequency
166MHz (*DDR333)
133MHz (*DDR266:2-2-2)
133MHz (*DDR266A)
133MHz (*DDR266B)
100MHz (*DDR200)
Interface
SSTL_2
Form Pactor
200pin Unbuffered SO-DIMM
* JEDEC Defined Specifications compliant
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.2/Oct. 02
1