HY57V64420HG Datasheet, PDF (7/11 Pages) Hynix Semiconductor – 4 Banks x 4M x 4Bit Synchronous DRAM

HY57V64420HG
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Parameter
System clock
cycle time
CAS Latency = 3
CAS Latency = 2
Clock high pulse width
Clock low pulse width
Access time from
clock
CAS Latency = 3
CAS Latency = 2
Data-out hold time
Data-Input setup time
Data-Input hold time
Address setup time
Address hold time
CKE setup time
CKE hold time
Command setup time
Command hold time
CLK to data output in low Z-time
CLK to data output ^{CAS Latency = 3}
in high Z-time
CAS Latency = 2
Symbol
-6
Min Max
-7
Min Max
-K
Min Max
-H
Min Max
-P
Min Max
-S
Min Max
tCK3
tCK2
6
7
7.5
7.5
10
10
1000
1000
1000
1000
1000
1000
10
10
7.5
10
10
12
tCHW
2.5
-
2.5
-
2.5
-
2.5
-
3
-
3
-
tCLW
2.5
-
2.5
-
2.5
-
2.5
-
3
-
3
-
tAC3
- 5.4
-
5.4
-
5.4
5.4
6
-
6
tAC2
-
6
-
6
-
5.4
6
-
6
-
8
tOH
2.7
-
2.7
-
2.7
-
2.7
-
3
-
3
-
tDS
1.5
-
1.5
-
1.5
-
1.5
-
2
-
2
-
tDH
0.8
-
0.8
-
0.8
-
0.8
-
1
-
1
-
tAS
1.5
-
1.5
-
1.5
-
1.5
-
2
-
2
-
tAH
0.8
-
0.8
-
0.8
-
0.8
-
1
-
1
-
tCKS
1.5
-
1.5
-
1.5
-
1.5
-
2
-
2
-
tCKH
0.8
-
0.8
-
0.8
-
0.8
-
1
-
1
-
tCS
1.5
-
1.5
-
1.5
-
1.5
-
2
-
2
-
tCH
0.8
-
0.8
-
0.8
-
0.8
-
1
-
1
-
tOLZ
1
-
1.5
-
1.5
-
1.5
-
1
-
2
-
tOHZ3
5.4
5.4
5.4
5.4
6
6
tOHZ2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
1
1
2
1
1
1
1
1
1
1
1
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate
Rev. 0.4/Nov. 01
7