HY29F400A Datasheet, PDF (7/40 Pages) Hynix Semiconductor – 4 Megabit (512Kx8/256Kx16) 5 Volt-only Flash Memory

HY29F400A
Table 3. HY29F400A Bus Operations Requiring High Voltage ^{1, 2}
Operation ³
CE# OE# WE# RESET# A[17:12] A[9] A[6] A[1] A[0]
DQ[7:0]
DQ[15:8]
BYTE# BYTE#
=H =L⁵
Sector Protect
L V_ID X
H
SA ⁴ V_ID X X X
X
X High-Z
Sector Unprotect
V_ID V_ID X
H
X
V_ID X X X
X
X High-Z
Temporary Sector
Unprotect
X
X
X
V_ID
X
XXXX
D_IN
D_IN High-Z
Manufacturer Code L L H
H
X
V_ID L
L
L
0xAD
X High-Z
Device ^HY29F400AB
Code _HY29F400AT
L
L
H
H
0xAB
X
V_ID L
L
H
0x23
0x22 High-Z
Sector Group
Protection
Verification
LLH
H
SA ⁴ V_ID L
H
Notes:
1. L = V_IL, H = V_IH, X = Don’t Care. See DC Characteristics for voltage levels.
2. Address bits not specified are Don’t Care.
3. See text for additional information.
4. SA = sector address. See Table 1.
5. DQ[15] is the A[-1] input in Byte Mode (BYTE# = L).
0x00 =
Unprotected
L
X
0x01 =
Protected
High-Z
The ‘Device Commands’ section of this document
provides details on the specific device commands
implemented in the HY29F400A.
Output Disable Operation
When the OE# input is at V_IH, output data from the
device is disabled and the data bus pins are placed
in the high impedance state.
Standby Operation
the HY29F400A will be in the RESET# TTL
Standby mode, but the standby current will be
greater. See Hardware Reset Operation section
for additional information on the reset operation.
The device requires standard access time (t_CE) for
read access when the device is in either of the
standby modes, before it is ready to read data. If
the device is deselected during erasure or pro-
gramming, it continues to draw active current until
the operation is completed.
When the system is not reading from or writing to
the HY29F400A, it can place the device in the
Standby mode. In this mode, current consump-
tion is greatly reduced, and the data bus outputs
are placed in the high impedance state, indepen-
dent of the OE# input. The Standby mode can be
invoked using two methods.
The device enters the CE# CMOS Standby mode
if the CE# and RESET# pins are both held at V_CC
± 0.5V. Note that this is a more restricted voltage
range than V_IH. If both CE# and RESET# are held
High, but not within V_CC ± 0.5V, the device will be
in the CE# TTL Standby mode, but the standby
current will be greater.
The device enters the RESET# CMOS Standby
mode when the RESET# pin is held at V_SS ± 0.5V.
If RESET# is held Low but not within V_SS ± 0.5V,
Hardware Reset Operation
The RESET# pin provides a hardware method of
resetting the device to reading array data. When
the RESET# pin is driven Low for the minimum
specified period, the device immediately termi-
nates any operation in progress, tri-states the data
bus pins, and ignores all read/write commands for
the duration of the RESET# pulse. The device also
resets the internal state machine to reading array
data. If an operation was interrupted by the as-
sertion of RESET#, it should be reinitiated once
the device is ready to accept another command
sequence to ensure data integrity.
Current is reduced for the duration of the RESET#
pulse as described in the Standby Operation sec-
tion above.
Rev. 1.0/Jan. 02
7