H5GQ1H24AFR Datasheet, PDF (66/173 Pages) Hynix Semiconductor – 1Gb (32Mx32) GDDR5 SGRAM

H5GQ1H24AFR
CK#
CK
CMD NOP
PRE
ALL
NOP
t_RP
MRS
NOP
t_MRD
A.C.
NOP
Old Setting Updating Setting New Setting
A.C. = any command allowed in bank idle state
Figure 37. Mode Register Set Timings
5.5. ACTIVATION
Before any READ or WRITE commands can be issued to a bank in the GDDR5 SGRAM, a row in that bank
must be “opened”. This is accomplished by the ACTIVE command (see Figure 38): BA0 ‐BA3 select the
bank, and A0‐A11 (A12) select the row to be activated. Once a row is open, a READ or WRITE command
could be issued to that row, subject to the t_RCD specification.
A subsequent ACTIVE command to another row in the same bank can only be issued after the previous
row has been closed (precharged). The minimum time interval between two successive ACTIVE com‐
mands on the same bank is defined by t_RC. A minimum time, t_RAS, must have elapsed between opening
and closing a row.
A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed,
which results in a reduction of total row‐access overhead. The minimum time interval between two suc‐
cessive ACTIVE commands on different banks to different bank groups is defined by t_RRDS. With bank
groups enabled, the minimum time interval between two successive ACTIVE commands to different
banks in the same bank group is defined by t_RRDL. In all other cases the interval is defined by t_RRDS.
<Link>Figure shows the t_RCD and t_RRD definition.
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009
66