H5GQ1H24AFR Datasheet, PDF (45/173 Pages) Hynix Semiconductor – 1Gb (32Mx32) GDDR5 SGRAM

H5GQ1H24AFR
4.2. MODE REGISTER 1 (MR1)
Mode Register 1 controls functions like drive strength, data termination, address/command termination,
Read DBI, Write DBI, ABI, control of calibration updates and PLL as shown in Figure 24.
The register is programmed via the MODE REGISTER SET (MRS) command with BA0=1, BA1=0, BA2=0
and BA3=0. Bits A0‐A1, A4‐A6 and A10 of this register are initialized with’0’s.
BA3 BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0
0
0
1
0
PLL
Reset
ABI WDBI RDBI PLL
Cal ADR/CMD Data
Upd Termination Termination
Driver
Strength
A11 PLL Reset
0
No
1
Yes
A7
PLL
0
Off
1
On
A1 A0 Driver Strength
0
0 Auto Calibration On
0
1
RFU
1
0
Nominal (60/40)
1
1
RFU
A10
ABI
0
On
1
Off
A9 Write DBI
0
On
1
Off
A6 Calibration Update
0
On
1
Off
A3 A2 Data Termination
0
0
0
1
1
0
1
1
Disabled
ZQ/2
ZQ
RFU
A8 Read DBI
0
On
1
Off
A5 A4 ADD/CMD Termination
0
0
CKE# value at Reset
0
1
ZQ/2
1
0
ZQ
1
1
Disabled
Figure 24. Mode Register 1 (MR1) Definition
Impedance Autocalibration of Output Buffer and Active Terminator
GDDR5 SGRAMs offer autocalibrating impedance output buffers and on‐die terminations. This enables a
user to match the driver impedance and terminations to the system within a given range. To adjust the
impedance, an external precision resistor is connected between the ZQ pin and V_SSQ. A nominal resistor
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009
45